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2021-07-20 16:39:56 +08:00

11 lines
229 B
VHDL

-- generated by newgenasym Thu Jul 15 13:15:42 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity socket2 is
port (
GND: INOUT STD_LOGIC;
\v+\: INOUT STD_LOGIC);
end socket2;