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14 lines
331 B
VHDL
14 lines
331 B
VHDL
-- generated by newgenasym Thu Jul 15 19:04:37 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity socket5 is
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port (
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\+5v\: INOUT STD_LOGIC;
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\3v3\: INOUT STD_LOGIC;
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GND: INOUT STD_LOGIC;
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RXD: INOUT STD_LOGIC;
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TXD: INOUT STD_LOGIC);
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end socket5;
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