mirror of
https://github.com/Jimmy-Bots/Short-Term.git
synced 2026-03-28 19:13:34 +00:00
18 lines
245 B
Verilog
18 lines
245 B
Verilog
// generated by newgenasym Thu Jul 15 20:13:24 2021
|
|
|
|
|
|
module socket6 (en, gnd, rxd, state, txd, vcc);
|
|
inout en;
|
|
inout gnd;
|
|
inout rxd;
|
|
inout state;
|
|
inout txd;
|
|
inout vcc;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|