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15 lines
365 B
VHDL
15 lines
365 B
VHDL
-- generated by newgenasym Thu Jul 15 20:13:24 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity socket6 is
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port (
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EN: INOUT STD_LOGIC;
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GND: INOUT STD_LOGIC;
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RXD: INOUT STD_LOGIC;
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STATE: INOUT STD_LOGIC;
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TXD: INOUT STD_LOGIC;
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VCC: INOUT STD_LOGIC);
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end socket6;
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