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57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
// generated by newgenasym Tue Jul 13 15:28:18 2021
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module stc89c52 (ale, \ea* , gnd, \p0.0/ad0 , \p0.1/ad1 , \p0.2/ad2 , \p0.3/ad3 ,
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\p0.4/ad4 , \p0.5/ad5 , \p0.6/ad6 , \p0.7/ad7 , \p1.0/t2 , \p1.1/t2ex ,
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\p1.2 , \p1.3 , \p1.4 , \p1.5 , \p1.6 , \p1.7 , \p2.0/a8 , \p2.1/a9 ,
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\p2.2/a10 , \p2.3/a11 , \p2.4/a12 , \p2.5/a13 , \p2.6/a14 , \p2.7/a15 ,
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\p3.0/rxd , \p3.1/txd , \p3.2/into* , \p3.3/int1* , \p3.4/to ,
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\p3.5/t1 , \p3.6/wr* , \p3.7/rd* , \psen* , rst, vcc, xtal1, xtal2);
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inout ale;
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inout \ea* ;
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inout gnd;
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inout \p0.0/ad0 ;
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inout \p0.1/ad1 ;
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inout \p0.2/ad2 ;
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inout \p0.3/ad3 ;
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inout \p0.4/ad4 ;
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inout \p0.5/ad5 ;
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inout \p0.6/ad6 ;
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inout \p0.7/ad7 ;
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inout \p1.0/t2 ;
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inout \p1.1/t2ex ;
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inout \p1.2 ;
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inout \p1.3 ;
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inout \p1.4 ;
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inout \p1.5 ;
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inout \p1.6 ;
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inout \p1.7 ;
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inout \p2.0/a8 ;
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inout \p2.1/a9 ;
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inout \p2.2/a10 ;
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inout \p2.3/a11 ;
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inout \p2.4/a12 ;
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inout \p2.5/a13 ;
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inout \p2.6/a14 ;
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inout \p2.7/a15 ;
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inout \p3.0/rxd ;
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inout \p3.1/txd ;
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inout \p3.2/into* ;
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inout \p3.3/int1* ;
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inout \p3.4/to ;
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inout \p3.5/t1 ;
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inout \p3.6/wr* ;
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inout \p3.7/rd* ;
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inout \psen* ;
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inout rst;
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inout vcc;
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inout xtal1;
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inout xtal2;
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initial
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begin
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end
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endmodule
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