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49 lines
1.5 KiB
VHDL
49 lines
1.5 KiB
VHDL
-- generated by newgenasym Tue Jul 13 15:28:18 2021
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity stc89c52 is
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port (
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ALE: INOUT STD_LOGIC;
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\ea*\: INOUT STD_LOGIC;
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GND: INOUT STD_LOGIC;
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\p0.0/ad0\: INOUT STD_LOGIC;
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\p0.1/ad1\: INOUT STD_LOGIC;
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\p0.2/ad2\: INOUT STD_LOGIC;
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\p0.3/ad3\: INOUT STD_LOGIC;
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\p0.4/ad4\: INOUT STD_LOGIC;
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\p0.5/ad5\: INOUT STD_LOGIC;
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\p0.6/ad6\: INOUT STD_LOGIC;
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\p0.7/ad7\: INOUT STD_LOGIC;
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\p1.0/t2\: INOUT STD_LOGIC;
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\p1.1/t2ex\: INOUT STD_LOGIC;
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\p1.2\: INOUT STD_LOGIC;
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\p1.3\: INOUT STD_LOGIC;
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\p1.4\: INOUT STD_LOGIC;
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\p1.5\: INOUT STD_LOGIC;
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\p1.6\: INOUT STD_LOGIC;
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\p1.7\: INOUT STD_LOGIC;
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\p2.0/a8\: INOUT STD_LOGIC;
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\p2.1/a9\: INOUT STD_LOGIC;
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\p2.2/a10\: INOUT STD_LOGIC;
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\p2.3/a11\: INOUT STD_LOGIC;
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\p2.4/a12\: INOUT STD_LOGIC;
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\p2.5/a13\: INOUT STD_LOGIC;
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\p2.6/a14\: INOUT STD_LOGIC;
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\p2.7/a15\: INOUT STD_LOGIC;
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\p3.0/rxd\: INOUT STD_LOGIC;
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\p3.1/txd\: INOUT STD_LOGIC;
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\p3.2/into*\: INOUT STD_LOGIC;
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\p3.3/int1*\: INOUT STD_LOGIC;
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\p3.4/to\: INOUT STD_LOGIC;
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\p3.5/t1\: INOUT STD_LOGIC;
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\p3.6/wr*\: INOUT STD_LOGIC;
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\p3.7/rd*\: INOUT STD_LOGIC;
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\psen*\: INOUT STD_LOGIC;
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RST: INOUT STD_LOGIC;
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VCC: INOUT STD_LOGIC;
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XTAL1: INOUT STD_LOGIC;
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XTAL2: INOUT STD_LOGIC);
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end stc89c52;
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