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2021-07-20 16:39:56 +08:00

13 lines
295 B
VHDL

-- generated by newgenasym Thu Jul 15 13:45:59 2021
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity switch is
port (
\1\: INOUT STD_LOGIC;
\2\: INOUT STD_LOGIC;
\3\: INOUT STD_LOGIC;
\4\: INOUT STD_LOGIC);
end switch;