diff --git a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xml b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xml
index 49746427..357e5423 100644
--- a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xml
+++ b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xml
@@ -23004,7 +23004,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Tue Mar 07 02:50:09 UTC 2023</spirit:value>
+            <spirit:value>Sun May 07 20:53:22 UTC 2023</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
diff --git a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/imports/hdl/dso_top.v b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/imports/hdl/dso_top.v
index b412d0c6..237bf4fc 100644
--- a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/imports/hdl/dso_top.v
+++ b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.srcs/sources_1/imports/hdl/dso_top.v
@@ -79,6 +79,7 @@ module dso_top
   reg[63:0] adc_data;	
   wire serdes_ready;
   
+  assign term = gpio_io_o_0[15:12];
   assign atten = gpio_io_o_0[19:16];
   assign dc_cpl = gpio_io_o_0[23:20];
    
diff --git a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.xpr b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.xpr
index 3bc051b5..df63926f 100644
--- a/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.xpr
+++ b/Firmware/dso_top_TE0712_Rev3_Baseboard/TE0712_Rev3_Baseboard.xpr
@@ -73,8 +73,11 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
-          <Proxy FileSetName="design_1_xdma_0_0"/>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
+          <Proxy FileSetName="design_1_util_ds_buf_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
+          <Proxy FileSetName="design_1_axi_crossbar_0_1"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
           <Proxy FileSetName="design_1_clk_wiz_0_0"/>
@@ -82,33 +85,30 @@
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_clock_converter_0_0/design_1_axi_clock_converter_0_0.xci">
           <Proxy FileSetName="design_1_axi_clock_converter_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
-          <Proxy FileSetName="design_1_axi_crossbar_0_0"/>
-        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_gpio_0_1/design_1_axi_gpio_0_1.xci">
           <Proxy FileSetName="design_1_axi_gpio_0_1"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
-          <Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
-          <Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_1/design_1_axi_crossbar_0_1.xci">
-          <Proxy FileSetName="design_1_axi_crossbar_0_1"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
-          <Proxy FileSetName="design_1_axi_datamover_0_0"/>
-        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0.xci">
           <Proxy FileSetName="design_1_mig_7series_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_ds_buf_0_0/design_1_util_ds_buf_0_0.xci">
-          <Proxy FileSetName="design_1_util_ds_buf_0_0"/>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_crossbar_0_0/design_1_axi_crossbar_0_0.xci">
+          <Proxy FileSetName="design_1_axi_crossbar_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_datamover_0_0/design_1_axi_datamover_0_0.xci">
+          <Proxy FileSetName="design_1_axi_datamover_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_dwidth_converter_0_0/design_1_axi_dwidth_converter_0_0.xci">
+          <Proxy FileSetName="design_1_axi_dwidth_converter_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_axi_fifo_mm_s_0_0/design_1_axi_fifo_mm_s_0_0.xci">
+          <Proxy FileSetName="design_1_axi_fifo_mm_s_0_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_0_0/design_1_util_vector_logic_0_0.xci">
           <Proxy FileSetName="design_1_util_vector_logic_0_0"/>
         </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_xdma_0_0/design_1_xdma_0_0.xci">
+          <Proxy FileSetName="design_1_xdma_0_0"/>
+        </CompFileExtendedInfo>
       </File>
       <File Path="$PSRCDIR/sources_1/imports/dso_top/I2C_Transmit.v">
         <FileInfo>
diff --git a/Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top_TE0712_Rev3_Baseboard.bin b/Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top_TE0712_Rev3_Baseboard.bin
index 80113097..add66216 100644
Binary files a/Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top_TE0712_Rev3_Baseboard.bin and b/Firmware/dso_top_TE0712_Rev3_Baseboard/dso_top_TE0712_Rev3_Baseboard.bin differ