-- generated by newgenasym Mon Sep 13 13:16:51 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity csmd0805 is
    port (    
	A:         IN     STD_LOGIC_VECTOR (0 DOWNTO 0);    
	B:         OUT    STD_LOGIC_VECTOR (0 DOWNTO 0));
end csmd0805;