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mirror of https://github.com/issus/altium-library.git synced 2025-04-02 03:36:35 +00:00

Create symbols/MCU - STM32/SCH - MCU - STM32 - ST MICROELECTRONICS STM32MP153CABX LFBGA354.SchLib

This commit is contained in:
Mark 2023-06-28 03:43:24 +01:00
parent 135d655ec2
commit 42d559e0d2

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ST MICROELECTRONICS STM32MP153CABX LFBGA354
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VSS_USBHS U13 VSS_USBHS U14 VSS_USBHS V12 VSS_USBHS V15 VSS_PLL2 F13 VSS_PLL J4 VSS_ANA L4 VSS A1 VSS A19 VSS B2 VSS B6 VSS C3 VSS C12 VSS C13 VSS C14 VSS C15 VSS C16 VSS C17 VSS D1 VSS D4 VSS D5 VSS D8 VSS E2 VSS E4 VSS E5 VSS E6 VSS E8 VSS E10 VSS E12 VSS E14 VSS E16 VSS F5 VSS F7 VSS F9 VSS F11 VSS F15 VSS G2 VSS G4 VSS G6 VSS G8 VSS G10 VSS G12 VSS G14 VSS H5 VSS H7 VSS H9 VSS H11 VSS H13 VSS H15 VSS J3 VSS J6 VSS J8 VSS J10 VSS J12 VSS J14 VSS K2 VSS K5 VSS K7 VSS K9 VSS K11 VSS K13 VSS K15 VSS L6 VSS L8 VSS L10 VSS L12 VSS L14 VSS M5 VSS M7 VSS M9 VSS M11 VSS M13 VSS M15 VSS N6 VSS N8 VSS N10 VSS N12 VSS N14 VSS P7 VSS P9 VSS P11 VSS P13 VSS P15 VSS R2 VSS R6 VSS R8 VSS R10 VSS R12 VSS R14 VSS R16 VSS T4 VSS U3 VSS U6 VSS U8 VSS U17 VSS W1 VSS W19 VSSA N4 VSSA P5 VSSA R5 VDDQ_DDR E15 VDDQ_DDR F14 VDDQ_DDR G15 VDDQ_DDR H14 VDDQ_DDR J15 VDDQ_DDR K14 VDDQ_DDR L15 VDDQ_DDR M14 VDDQ_DDR N15 VDDQ_DDR P14 VDDQ_DDR R15 VDDCORE E7 VDDCORE E9 VDDCORE E11 VDDCORE E13 VDDCORE F4 VDDCORE F6 VDDCORE F8 VDDCORE F10 VDDCORE F12 VDDCORE G5 VDDCORE G7 VDDCORE G9 VDDCORE G11 VDDCORE H4 VDDCORE H6 VDDCORE H8 VDDCORE H10 VDDCORE H12 VDDCORE J7 VDDCORE J9 VDDCORE J11 VDDCORE J13 VDDCORE K8 VDDCORE K10 VDDCORE K12 VDDCORE L9 VDDCORE L11 VDDCORE L13 VDDCORE M10 VDDCORE M12 VDDCORE N11 VDDCORE N13 VDDCORE P12 VDDCORE R13 VDD3V3_USBHS W12 VDD3V3_USBFS W15 VDD1V2_Unused A16 VDD1V2_Unused B16 VDD_Unused A12 VDD_PLL2 G13 VDD_PLL J5 VDD_ANA L3 VDD K6 VDD L5 VDD L7 VDD M6 VDD M8 VDD N5 VDD N7 VDD N9 VDD P6 VDD P8 VDD P10 VDD R7 VDD R9 VDD R11 VDDA1V8_Unused B12 VDDA1V8_REG V11 VDDA1V1_REG W11 VDDA M4 VBAT H3 VREF+ N3 VREF- M3 NRST J1 BOOT2 L2 BOOT1 K4 BOOT0 K1 PDR_ON N2 VSS_USBHS U13 VSS_USBHS U14 VSS_USBHS V12 VSS_USBHS V15 VSS_PLL2 F13 VSS_PLL J4 VSS_ANA L4 VSS A1 VSS A19 VSS B2 VSS B6 VSS C3 VSS C12 VSS C13 VSS C14 VSS C15 VSS C16 VSS C17 VSS D1 VSS D4 VSS D5 VSS D8 VSS E2 VSS E4 VSS E5 VSS E6 VSS E8 VSS E10 VSS E12 VSS E14 VSS E16 VSS F5 VSS F7 VSS F9 VSS F11 VSS F15 VSS G2 VSS G4 VSS G6 VSS G8 VSS G10 VSS G12 VSS G14 VSS H5 VSS H7 VSS H9 VSS H11 VSS H13 VSS H15 VSS J3 VSS J6 VSS J8 VSS J10 VSS J12 VSS J14 VSS K2 VSS K5 VSS K7 VSS K9 VSS K11 VSS K13 VSS K15 VSS L6 VSS L8 VSS L10 VSS L12 VSS L14 VSS M5 VSS M7 VSS M9 VSS M11 VSS M13 VSS M15 VSS N6 VSS N8 VSS N10 VSS N12 VSS N14 VSS P7 VSS P9 VSS P11 VSS P13 VSS P15 VSS R2 VSS R6 VSS R8 VSS R10 VSS R12 VSS R14 VSS R16 VSS T4 VSS U3 VSS U6 VSS U8 VSS U17 VSS W1 VSS W19 VSSA N4 VSSA P5 VSSA R5 VDDQ_DDR E15 VDDQ_DDR F14 VDDQ_DDR G15 VDDQ_DDR H14 VDDQ_DDR J15 VDDQ_DDR K14 VDDQ_DDR L15 VDDQ_DDR M14 VDDQ_DDR N15 VDDQ_DDR P14 VDDQ_DDR R15 VDDCORE E7 VDDCORE E9 VDDCORE E11 VDDCORE E13 VDDCORE F4 VDDCORE F6 VDDCORE F8 VDDCORE F10 VDDCORE F12 VDDCORE G5 VDDCORE G7 VDDCORE G9 VDDCORE G11 VDDCORE H4 VDDCORE H6 VDDCORE H8 VDDCORE H10 VDDCORE H12 VDDCORE J7 VDDCORE J9 VDDCORE J11 VDDCORE J13 VDDCORE K8 VDDCORE K10 VDDCORE K12 VDDCORE L9 VDDCORE L11 VDDCORE L13 VDDCORE M10 VDDCORE M12 VDDCORE N11 VDDCORE N13 VDDCORE P12 VDDCORE R13 VDD3V3_USBHS W12 VDD3V3_USBFS W15 VDD1V2_Unused A16 VDD1V2_Unused B16 VDD_Unused A12 VDD_PLL2 G13 VDD_PLL J5 VDD_ANA L3 VDD K6 VDD L5 VDD L7 VDD M6 VDD M8 VDD N5 VDD N7 VDD N9 VDD P6 VDD P8 VDD P10 VDD R7 VDD R9 VDD R11 VDDA1V8_Unused B12 VDDA1V8_REG V11 VDDA1V1_REG W11 VDDA M4 VBAT H3 VREF+ N3 VREF- M3 NRST J1 BOOT2 L2 BOOT1 K4 BOOT0 K1 PDR_ON N2
BYPASS_REG1V8 T15 DDR_A0/DDR_A0 H18 DDR_A1/DDR_A1 M17 DDR_A10/DDR_A10 M19 DDR_A11/DDR_A11 M18 DDR_A12/DDR_A12 L17 DDR_A13/DDR_A13 F17 DDR_A14/DDR_A14 N18 DDR_A15/DDR_A15 L16 DDR_A2/DDR_A2 G18 DDR_A3/DDR_A3 F19 DDR_A4/DDR_A4 P17 DDR_A5/DDR_A5 H17 DDR_A6/DDR_A6 N16 DDR_A7/DDR_A7 E17 DDR_A8/DDR_A8 R17 DDR_A9/DDR_A9 G17 DDR_ATO/DDR_ATO N19 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G19 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ N17 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ J16 DDR_CASN/DDR_CASN K17 DDR_CKE/DDR_CKE P19 DDR_CLKN/DDR_CLKN K19 DDR_CLKP/DDR_CLKP L19 DDR_CSN/DDR_CSN J18 DDR_DQ0/DDR_DQ0 A17 DDR_DQ1/DDR_DQ1 A18 DDR_DQ10/DDR_DQ10 R18 DDR_DQ11/DDR_DQ11 V19 DDR_DQ12/DDR_DQ12 W18 DDR_DQ13/DDR_DQ13 T18 DDR_DQ14/DDR_DQ14 V18 DDR_DQ15/DDR_DQ15 W17 DDR_DQ2/DDR_DQ2 D18 DDR_DQ3/DDR_DQ3 B17 DDR_DQ4/DDR_DQ4 E18 DDR_DQ5/DDR_DQ5 D17 DDR_DQ6/DDR_DQ6 D19 DDR_DQ7/DDR_DQ7 B18 DDR_DQ8/DDR_DQ8 P18 DDR_DQ9/DDR_DQ9 T17 DDR_DQM0/DDR_DQM0 C18 DDR_DQM1/DDR_DQM1 U18 DDR_DQS0N/DDR_DQS0N B19 DDR_DQS0P/DDR_DQS0P C19 DDR_DQS1N/DDR_DQS1N T19 DDR_DQS1P/DDR_DQS1P U19 DDR_DTO0/DDR_DTO0 K18 DDR_DTO1/DDR_DTO1 J19 DDR_ODT/DDR_ODT H19 DDR_RASN/DDR_RASN L18 DDR_RESETN/DDR_RESETN G16 DDR_VREF/DDR_VREF W16 DDR_WEN/DDR_WEN J17 DDR_ZQ/DDR_ZQ F18 DNU A13 DNU A14 DNU A15 DNU B13 DNU B14 DNU B15 JTCK-SWCLK/DEBUG_JTCK-SWCLK D16 JTDI/DEBUG_JTDI D13 JTDO-TRACESWO/DEBUG_JTDO-SWO D14 JTMS-SWDIO/DEBUG_JTMS-SWDIO D15 NJTRST/DEBUG_JTRST D12 NRST_CORE J2 OTG_VBUS/USB_OTG_HS_VBUS U15 PDR_ON_CORE N1 PWR_LP P1 PWR_ON L1 USB_DM1/USBH_HS1_DM W14 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM V13 USB_DP1/USBH_HS1_DP V14 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP W13 USB_RREF V16 BYPASS_REG1V8 T15 DDR_A0/DDR_A0 H18 DDR_A1/DDR_A1 M17 DDR_A10/DDR_A10 M19 DDR_A11/DDR_A11 M18 DDR_A12/DDR_A12 L17 DDR_A13/DDR_A13 F17 DDR_A14/DDR_A14 N18 DDR_A15/DDR_A15 L16 DDR_A2/DDR_A2 G18 DDR_A3/DDR_A3 F19 DDR_A4/DDR_A4 P17 DDR_A5/DDR_A5 H17 DDR_A6/DDR_A6 N16 DDR_A7/DDR_A7 E17 DDR_A8/DDR_A8 R17 DDR_A9/DDR_A9 G17 DDR_ATO/DDR_ATO N19 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G19 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ N17 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ J16 DDR_CASN/DDR_CASN K17 DDR_CKE/DDR_CKE P19 DDR_CLKN/DDR_CLKN K19 DDR_CLKP/DDR_CLKP L19 DDR_CSN/DDR_CSN J18 DDR_DQ0/DDR_DQ0 A17 DDR_DQ1/DDR_DQ1 A18 DDR_DQ10/DDR_DQ10 R18 DDR_DQ11/DDR_DQ11 V19 DDR_DQ12/DDR_DQ12 W18 DDR_DQ13/DDR_DQ13 T18 DDR_DQ14/DDR_DQ14 V18 DDR_DQ15/DDR_DQ15 W17 DDR_DQ2/DDR_DQ2 D18 DDR_DQ3/DDR_DQ3 B17 DDR_DQ4/DDR_DQ4 E18 DDR_DQ5/DDR_DQ5 D17 DDR_DQ6/DDR_DQ6 D19 DDR_DQ7/DDR_DQ7 B18 DDR_DQ8/DDR_DQ8 P18 DDR_DQ9/DDR_DQ9 T17 DDR_DQM0/DDR_DQM0 C18 DDR_DQM1/DDR_DQM1 U18 DDR_DQS0N/DDR_DQS0N B19 DDR_DQS0P/DDR_DQS0P C19 DDR_DQS1N/DDR_DQS1N T19 DDR_DQS1P/DDR_DQS1P U19 DDR_DTO0/DDR_DTO0 K18 DDR_DTO1/DDR_DTO1 J19 DDR_ODT/DDR_ODT H19 DDR_RASN/DDR_RASN L18 DDR_RESETN/DDR_RESETN G16 DDR_VREF/DDR_VREF W16 DDR_WEN/DDR_WEN J17 DDR_ZQ/DDR_ZQ F18 DNU A13 DNU A14 DNU A15 DNU B13 DNU B14 DNU B15 JTCK-SWCLK/DEBUG_JTCK-SWCLK D16 JTDI/DEBUG_JTDI D13 JTDO-TRACESWO/DEBUG_JTDO-SWO D14 JTMS-SWDIO/DEBUG_JTMS-SWDIO D15 NJTRST/DEBUG_JTRST D12 NRST_CORE J2 OTG_VBUS/USB_OTG_HS_VBUS U15 PDR_ON_CORE N1 PWR_LP P1 PWR_ON L1 USB_DM1/USBH_HS1_DM W14 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM V13 USB_DP1/USBH_HS1_DP V14 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP W13 USB_RREF V16
PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 R3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 U4 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 W2 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX P3 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 R4 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 P4 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 T5 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 T6 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B8 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX C8 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID T16 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 V17 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS U16 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX P2 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 R1 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 C7 PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 R3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 U4 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 W2 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX P3 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 R4 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 P4 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 T5 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 T6 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B8 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX C8 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID T16 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 V17 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS U16 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX P2 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 R1 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 C7
PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 W3 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N V3 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 T13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 A7 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 B9 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 T8 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 T12 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX B5 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 W6 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 D9 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 W5 PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 V1 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 V5 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 T9 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 C9 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 A8 PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 W3 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N V3 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 T13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 A7 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 B9 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 T8 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 T12 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX B5 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 W6 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 D9 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 W5 PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 V1 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 V5 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 T9 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 C9 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 A8
PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ T7 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP V2 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO T2 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI T3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 W4 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX V4 PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 D10 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 A9 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK C11 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 A10 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 D11 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 A11 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 C10 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 K3 PC14-OSC32_IN/RCC_OSC32_IN H1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT H2 PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ T7 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP V2 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO T2 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI T3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 W4 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX V4 PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 D10 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 A9 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK C11 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 A10 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 D11 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 A11 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 C10 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 K3 PC14-OSC32_IN/RCC_OSC32_IN H1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT H2
PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A3 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A4 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX B10 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 C6 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS D6 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX D7 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 E3 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK B4 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX F2 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX G3 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 C5 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 V8 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 U11 PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 U12 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS F3 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS G1 PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A3 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A4 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX B10 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 C6 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS D6 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX D7 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 E3 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK B4 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX F2 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX G3 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 C5 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 V8 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 U11 PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 U12 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS F3 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS G1
PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C4 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX B1 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK T1 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ A5 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B11 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B7 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 B3 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX T10 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX T11 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS W7 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS V10 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 C1 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N D2 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 C2 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 D3 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 E1 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX V9 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX W8 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS U10 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS W9 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ U9 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI U5 PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C4 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX B1 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK T1 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ A5 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B11 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B7 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 B3 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX T10 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX T11 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS W7 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS V10 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 C1 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N D2 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 C2 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 D3 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 E1 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX V9 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX W8 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS U10 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS W9 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ U9 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI U5
PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ A6 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 W10 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 U7 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 T14 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS V7 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 V6 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 F1 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 U2 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 U1 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 A2 PH0-OSC_IN/RCC_OSC_IN M1 PH1-OSC_OUT/RCC_OSC_OUT M2 PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ A6 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 W10 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 U7 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 T14 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS V7 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 V6 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 F1 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 U2 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 U1 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 A2 PH0-OSC_IN/RCC_OSC_IN M1 PH1-OSC_OUT/RCC_OSC_OUT M2
ST MICROELECTRONICS STM32MP153CABX LFBGA354
Part ID
ST MICROELECTRONICS STM32MP153CABX LFBGA354
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