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mirror of https://github.com/issus/altium-library.git synced 2025-04-02 03:36:35 +00:00

Create symbols/MCU - STM32/SCH - MCU - STM32 - ST MICROELECTRONICS STM32MP153FADX TFBGA257.SchLib

This commit is contained in:
Mark 2023-06-28 04:05:20 +01:00
parent 7b4515395e
commit addb05c516

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ST MICROELECTRONICS STM32MP153FADX TFBGA257
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VSS A1 VSS A6 VSS A19 VSS C14 VSS D17 VSS F3 VSS F18 VSS G1 VSS G17 VSS K17 VSS K19 VSS N1 VSS N17 VSS R19 VSS U9 VSS W1 VSS W5 VSS W13 VSS W19 VSS 1A6 VSS 1B8 VSS 1C3 VSS 1C5 VSS 1C7 VSS 1D2 VSS 1D4 VSS 1D6 VSS 1E3 VSS 1E5 VSS 1E7 VSS 1F4 VSS 1F6 VSS 1G2 VSS 1G5 VSS 1G7 VSS 1H2 VSS 1H3 VSS 1H4 VSS 1H6 VSS 1H8 VSS 1J5 VSS 1J9 VSSA 1G1 VDDQ_DDR 1B9 VDDQ_DDR 1D9 VDDQ_DDR 1F9 VDDQ_DDR 1H9 VDDCORE 1B3 VDDCORE 1B5 VDDCORE 1C4 VDDCORE 1C6 VDDCORE 1D3 VDDCORE 1D5 VDDCORE 1D7 VDDCORE 1E4 VDDCORE 1E6 VDDCORE 1E8 VDDCORE 1F5 VDDCORE 1F7 VDDCORE 1G6 VDDCORE 1G8 VDD3V3_USB 1H7 VDD1V2_Unused 1A7 VDD1V2_Unused 1B7 VDD_Unused C13 VDD 1E2 VDD 1F3 VDD 1G3 VDD 1G4 VDD 1J3 VDDA1V8_Unused 1B6 VDDA1V8_REG 1H5 VDDA1V1_REG 1J6 VDDA 1F1 VDDA 1F2 VREF+ M3 VBAT 1D1 NRST E2 BOOT2 H1 BOOT1 K3 BOOT0 H3 PDR_ON L3 VSS A1 VSS A6 VSS A19 VSS C14 VSS D17 VSS F3 VSS F18 VSS G1 VSS G17 VSS K17 VSS K19 VSS N1 VSS N17 VSS R19 VSS U9 VSS W1 VSS W5 VSS W13 VSS W19 VSS 1A6 VSS 1B8 VSS 1C3 VSS 1C5 VSS 1C7 VSS 1D2 VSS 1D4 VSS 1D6 VSS 1E3 VSS 1E5 VSS 1E7 VSS 1F4 VSS 1F6 VSS 1G2 VSS 1G5 VSS 1G7 VSS 1H2 VSS 1H3 VSS 1H4 VSS 1H6 VSS 1H8 VSS 1J5 VSS 1J9 VSSA 1G1 VDDQ_DDR 1B9 VDDQ_DDR 1D9 VDDQ_DDR 1F9 VDDQ_DDR 1H9 VDDCORE 1B3 VDDCORE 1B5 VDDCORE 1C4 VDDCORE 1C6 VDDCORE 1D3 VDDCORE 1D5 VDDCORE 1D7 VDDCORE 1E4 VDDCORE 1E6 VDDCORE 1E8 VDDCORE 1F5 VDDCORE 1F7 VDDCORE 1G6 VDDCORE 1G8 VDD3V3_USB 1H7 VDD1V2_Unused 1A7 VDD1V2_Unused 1B7 VDD_Unused C13 VDD 1E2 VDD 1F3 VDD 1G3 VDD 1G4 VDD 1J3 VDDA1V8_Unused 1B6 VDDA1V8_REG 1H5 VDDA1V1_REG 1J6 VDDA 1F1 VDDA 1F2 VREF+ M3 VBAT 1D1 NRST E2 BOOT2 H1 BOOT1 K3 BOOT0 H3 PDR_ON L3
BYPASS_REG1V8 U11 DDR_A0/DDR_A0 G18 DDR_A1/DDR_A1 M19 DDR_A10/DDR_A10 M17 DDR_A11/DDR_A11 N19 DDR_A12/DDR_A12 M18 DDR_A13/DDR_A13 E17 DDR_A14/DDR_A14 N18 DDR_A15/DDR_A15 L18 DDR_A2/DDR_A2 F17 DDR_A3/DDR_A3 F19 DDR_A4/DDR_A4 R17 DDR_A5/DDR_A5 1C9 DDR_A6/DDR_A6 1G9 DDR_A7/DDR_A7 1A9 DDR_A8/DDR_A8 T17 DDR_A9/DDR_A9 E18 DDR_ATO/DDR_ATO 1F8 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G19 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ P18 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ H17 DDR_CASN/DDR_CASN J19 DDR_CKE/DDR_CKE P17 DDR_CLKN/DDR_CLKN K18 DDR_CLKP/DDR_CLKP L17 DDR_CSN/DDR_CSN J17 DDR_DQ0/DDR_DQ0 A17 DDR_DQ1/DDR_DQ1 A18 DDR_DQ10/DDR_DQ10 T19 DDR_DQ11/DDR_DQ11 W18 DDR_DQ12/DDR_DQ12 W17 DDR_DQ13/DDR_DQ13 T18 DDR_DQ14/DDR_DQ14 U17 DDR_DQ15/DDR_DQ15 V17 DDR_DQ2/DDR_DQ2 C18 DDR_DQ3/DDR_DQ3 B16 DDR_DQ4/DDR_DQ4 D18 DDR_DQ5/DDR_DQ5 D19 DDR_DQ6/DDR_DQ6 C19 DDR_DQ7/DDR_DQ7 B17 DDR_DQ8/DDR_DQ8 R18 DDR_DQ9/DDR_DQ9 U19 DDR_DQM0/DDR_DQM0 C17 DDR_DQM1/DDR_DQM1 V18 DDR_DQS0N/DDR_DQS0N B18 DDR_DQS0P/DDR_DQS0P B19 DDR_DQS1N/DDR_DQS1N U18 DDR_DQS1P/DDR_DQS1P V19 DDR_DTO0/DDR_DTO0 1D8 DDR_DTO1/DDR_DTO1 1C8 DDR_ODT/DDR_ODT H18 DDR_RASN/DDR_RASN 1E9 DDR_RESETN/DDR_RESETN C16 DDR_VREF/DDR_VREF W16 DDR_WEN/DDR_WEN J18 DDR_ZQ/DDR_ZQ 1A8 DNU A12 DNU A13 DNU B11 DNU B12 DNU B13 DNU C12 JTCK-SWCLK/DEBUG_JTCK-SWCLK A16 JTDI/DEBUG_JTDI B15 JTDO-TRACESWO/DEBUG_JTDO-SWO A15 JTMS-SWDIO/DEBUG_JTMS-SWDIO C15 NJTRST/DEBUG_JTRST B14 NRST_CORE J3 OTG_VBUS/USB_OTG_HS_VBUS V16 PDR_ON_CORE K2 PWR_LP K1 PWR_ON M2 USB_DM1/USBH_HS1_DM W14 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM W10 USB_DP1/USBH_HS1_DP V14 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP V10 USB_RREF 1J8 BYPASS_REG1V8 U11 DDR_A0/DDR_A0 G18 DDR_A1/DDR_A1 M19 DDR_A10/DDR_A10 M17 DDR_A11/DDR_A11 N19 DDR_A12/DDR_A12 M18 DDR_A13/DDR_A13 E17 DDR_A14/DDR_A14 N18 DDR_A15/DDR_A15 L18 DDR_A2/DDR_A2 F17 DDR_A3/DDR_A3 F19 DDR_A4/DDR_A4 R17 DDR_A5/DDR_A5 1C9 DDR_A6/DDR_A6 1G9 DDR_A7/DDR_A7 1A9 DDR_A8/DDR_A8 T17 DDR_A9/DDR_A9 E18 DDR_ATO/DDR_ATO 1F8 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G19 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ P18 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ H17 DDR_CASN/DDR_CASN J19 DDR_CKE/DDR_CKE P17 DDR_CLKN/DDR_CLKN K18 DDR_CLKP/DDR_CLKP L17 DDR_CSN/DDR_CSN J17 DDR_DQ0/DDR_DQ0 A17 DDR_DQ1/DDR_DQ1 A18 DDR_DQ10/DDR_DQ10 T19 DDR_DQ11/DDR_DQ11 W18 DDR_DQ12/DDR_DQ12 W17 DDR_DQ13/DDR_DQ13 T18 DDR_DQ14/DDR_DQ14 U17 DDR_DQ15/DDR_DQ15 V17 DDR_DQ2/DDR_DQ2 C18 DDR_DQ3/DDR_DQ3 B16 DDR_DQ4/DDR_DQ4 D18 DDR_DQ5/DDR_DQ5 D19 DDR_DQ6/DDR_DQ6 C19 DDR_DQ7/DDR_DQ7 B17 DDR_DQ8/DDR_DQ8 R18 DDR_DQ9/DDR_DQ9 U19 DDR_DQM0/DDR_DQM0 C17 DDR_DQM1/DDR_DQM1 V18 DDR_DQS0N/DDR_DQS0N B18 DDR_DQS0P/DDR_DQS0P B19 DDR_DQS1N/DDR_DQS1N U18 DDR_DQS1P/DDR_DQS1P V19 DDR_DTO0/DDR_DTO0 1D8 DDR_DTO1/DDR_DTO1 1C8 DDR_ODT/DDR_ODT H18 DDR_RASN/DDR_RASN 1E9 DDR_RESETN/DDR_RESETN C16 DDR_VREF/DDR_VREF W16 DDR_WEN/DDR_WEN J18 DDR_ZQ/DDR_ZQ 1A8 DNU A12 DNU A13 DNU B11 DNU B12 DNU B13 DNU C12 JTCK-SWCLK/DEBUG_JTCK-SWCLK A16 JTDI/DEBUG_JTDI B15 JTDO-TRACESWO/DEBUG_JTDO-SWO A15 JTMS-SWDIO/DEBUG_JTMS-SWDIO C15 NJTRST/DEBUG_JTRST B14 NRST_CORE J3 OTG_VBUS/USB_OTG_HS_VBUS V16 PDR_ON_CORE K2 PWR_LP K1 PWR_ON M2 USB_DM1/USBH_HS1_DM W14 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM W10 USB_DP1/USBH_HS1_DP V14 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP V10 USB_RREF 1J8
PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 N3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 T1 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 T3 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX N2 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 1J1 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 1H1 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 W3 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 W2 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B8 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX C6 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID U16 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 U15 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS V15 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX L2 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 L1 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 B4 PA0/ADC1/ETH1/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/TIM8/UART4/USART2 N3 PA1/ADC1/ETH1/LPTIM3/LTDC/QUADSPI/SAI2/TIM15/TIM2/TIM5/UART4/USART2 T1 PA2/ADC1/ETH1/LPTIM4/LTDC/PWR/SAI2/SDMMC2/TIM15/TIM2/TIM5/USART2 T3 PA3/ADC1_INP15/ETH1_COL/LPTIM5_OUT/L\T\D\C\_\B\2\/L\T\D\C\_\B\5\/PWR_PVD_IN/TIM15_CH2/TIM2_CH4/TIM5_CH4/USART2_RX N2 PA4/ADC1/ADC2/DAC1/DCMI/HDP/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM5/USART2 1J1 PA5/ADC1/ADC2/DAC1/I2S1/LTDC/SAI4/SPI1/SPI6/TIM2/TIM8 1H1 PA6/ADC1/ADC2/DCMI/I2S1/LTDC/SAI4/SPI1/SPI6/TIM13/TIM1/TIM3/TIM8 W3 PA7/ADC1/ADC2/ETH1/I2S1/QUADSPI/SAI4/SPI1/SPI6/TIM14/TIM1/TIM3/TIM8 W2 PA8/I2C3/I2S3/LTDC/RCC/SAI4/SDMMC2/SPI3/TIM1/TIM8/UART7/USART1/USB B8 PA9/DAC1_EXTI9/DCMI_D0/I2C3_SMBA/I2S2_CK/LTDC_R5/SDMMC2_CDIR/SDMMC2_D5/SPI2_SCK/TIM1_CH2/USART1_TX C6 PA10/DCMI_D1/I2S3_WS/L\T\D\C\_\B\1\/S\A\I\4\_\F\S\_\B\/S\P\I\3\_\N\S\S\/TIM1_CH3/USART1_RX/USB_OTG_HS_ID U16 PA11/ADC1/ADC2/FDCAN1/I2C5/I2C6/I2S2/LTDC/SPI2/TIM1/UART4/USART1 U15 PA12/FDCAN1_TX/I2C5_SDA/I2C6_SDA/LTDC_R5/S\A\I\2\_\F\S\_\B\/TIM1_ETR/UART4_TX/USART1_DE/USART1_RTS V15 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX L2 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2 L1 PA15/CEC/ADC1/ADC2/DEBUG/I2S1/I2S3/LTDC/SAI4/SDMMC1/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART4/UART7 B4
PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 U2 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N U1 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 V13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 C7 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 B6 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 V5 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 W11 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX A3 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 V4 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 C9 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 U5 PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 U3 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 V3 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 1J2 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 1A4 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 C8 PB0/ADC1/ADC2/DFSDM1/ETH1/LTDC/TIM1/TIM3/TIM8/UART4 U2 PB1/ADC1_INP5/ADC2_INP5/DFSDM1_DATIN1/ETH1_RXD3/LTDC_G0/LTDC_R6/TIM1_CH3N/TIM3_CH4/TIM8_CH3N U1 PB2/DEBUG/DFSDM1/I2S3/I2S/QUADSPI/SAI1/SPI3/UART4/USART1 V13 PB3/DEBUG/I2S1/I2S3/SAI4/SDMMC2/SPI1/SPI3/SPI6/TIM2/UART7 C7 PB4/DEBUG/I2S1/I2S2/I2S3/SAI4/SDMMC2/SPI1/SPI2/SPI3/SPI6/TIM16/TIM3/UART7 B6 PB5/DCMI/ETH1/FDCAN2/I2C1/I2C4/I2S1/I2S3/LTDC/SAI4/SPI1/SPI3/SPI6/TIM17/TIM3/UART5 V5 PB6/CEC/DCMI/DFSDM1/FDCAN2/I2C1/I2C4/QUADSPI/TIM16/TIM4/UART5/USART1 W11 PB7/DCMI_VSYNC/DFSDM1_CKIN5/F\M\C\_\N\L\/I2C1_SDA/I2C4_SDA/SDMMC2_D1/TIM17_CH1N/TIM4_CH2/USART1_RX A3 PB8/DCMI/DFSDM1/ETH1/FDCAN1/HDP/I2C1/I2C4/LTDC/SDMMC1/SDMMC2/TIM16/TIM4/UART4 V4 PB9/DAC1/DCMI/DFSDM1/FDCAN1/HDP/I2C1/I2C4/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/TIM17/TIM4/UART4 C9 PB10/DFSDM1/ETH1/I2C2/I2S2/LPTIM2/LTDC/QUADSPI/SPI2/TIM2/USART3 U5 PB11/ADC1/ADC2/DFSDM1/ETH1/I2C2/LPTIM2/LTDC/TIM2/USART3 U3 PB12/DFSDM1/ETH1/FDCAN2/I2C2/I2C6/I2S2/SPI2/TIM1/UART5/USART3 V3 PB13/DFSDM1/ETH1/FDCAN2/I2S2/LPTIM2/SPI2/TIM1/UART5/USART3 1J2 PB14/DFSDM1/I2S2/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1/USART3 1A4 PB15/ADC1/ADC2/DFSDM1/I2S2/RTC/SDMMC2/SPI2/TIM12/TIM1/TIM8/USART1 C8
PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ U4 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP T2 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO P2 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI P3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 V2 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX V1 PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 A4 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 C10 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK A9 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 B9 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 B10 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 C11 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 1B4 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 G3 PC14-OSC32_IN/RCC_OSC32_IN G2 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT F2 PC0/ADC1_INP10/ADC2_INP10/DFSDM1_CKIN0/DFSDM1_DATIN4/LPTIM2_IN2/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\2\_\N\C\S\/S\A\I\2\_\F\S\_\B\ U4 PC1/ADC1/ADC2/DEBUG/DFSDM1/ETH1/I2S2/PWR/SAI1/SDMMC2/SPI2/TAMP T2 PC2/ADC1_INN11/ADC1_INP12/DCMI_PIXCLK/DFSDM1_CKIN1/DFSDM1_CKOUT/ETH1_TXD2/I2S2_SDI/SPI2_MISO P2 PC3/ADC1_INN12/ADC1_INP13/DEBUG_TRACECLK/DFSDM1_DATIN1/ETH1_TX_CLK/I2S2_SDO/SPI2_MOSI P3 PC4/ADC1_INP4/ADC2_INP4/DFSDM1_CKIN2/ETH1_RXD0/I2S1_MCK/SPDIFRX_IN2 V2 PC5/ADC1/ADC2/DFSDM1/ETH1/SAI1/SAI4/SPDIFRX V1 PC6/DCMI/DFSDM1/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 A4 PC7/DCMI/DFSDM1/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 C10 PC8/DCMI_D2/DEBUG_TRACED0/SDMMC1_D0/TIM3_CH3/TIM8_CH3/UART4_TX/UART5_DE/UART5_RTS/USART6_CK A9 PC9/DAC1/DCMI/DEBUG/I2C3/I2S/LTDC/QUADSPI/SDMMC1/TIM3/TIM8/UART5 B9 PC10/DCMI/DEBUG/DFSDM1/I2S3/LTDC/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 B10 PC11/ADC1/ADC2/DCMI/DEBUG/DFSDM1/I2S3/QUADSPI/SAI4/SDMMC1/SPI3/UART4/USART3 C11 PC12/DCMI/DEBUG/I2S3/RCC/SAI4/SDMMC1/SPI3/UART5/USART3 1B4 PC13/PWR_WKUP3/RTC_LSCO/RTC_TS/TAMP_IN1/TAMP_OUT2/TAMP_OUT3 G3 PC14-OSC32_IN/RCC_OSC32_IN G2 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT F2
PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 C5 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A2 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX 1A5 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 A7 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS C3 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX C4 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 1B1 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK B3 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX E1 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX 1C1 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 1A2 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 U8 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 U14 PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 U13 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS 1E1 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS 1C2 PD0/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 C5 PD1/DFSDM1/FDCAN1/FMC/I2C5/I2C6/SAI3/SDMMC3/UART4 A2 PD2/DCMI_D11/I2C5_SMBA/SDMMC1_CMD/TIM3_ETR/UART4_RX/UART5_RX 1A5 PD3/DCMI/DFSDM1/FMC/HDP/I2S2/LTDC/SDMMC1/SDMMC2/SPI2/USART2 A7 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/SAI3_FS_A/SDMMC3_D1/USART2_DE/USART2_RTS C3 PD5/F\M\C\_\N\W\E\/SDMMC3_D2/USART2_TX C4 PD6/DCMI/DFSDM1/FMC/I2S3/LTDC/SAI1/SPI3/TIM16/USART2 1B1 PD7/DEBUG_TRACED6/DFSDM1_CKIN1/DFSDM1_DATIN4/F\M\C\_\N\E\1\/I2C2_SCL/SDMMC3_D3/SPDIFRX_IN0/USART2_CK B3 PD8/DFSDM1_CKIN3/FMC_D13/FMC_DA13/L\T\D\C\_\B\7\/S\A\I\3\_\S\C\K\_\B\/SPDIFRX_IN1/USART3_TX E1 PD9/DAC1_EXTI9/DCMI_HSYNC/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/S\A\I\3\_\S\D\_\B\/USART3_RX 1C1 PD10/DFSDM1/FMC/I2C5/I2S3/LTDC/RTC/SAI3/SPI3/TIM16/USART3 1A2 PD11/ADC1/ADC2/FMC/I2C1/I2C4/LPTIM2/QUADSPI/SAI2/USART3 U8 PD12/FMC/I2C1/I2C4/LPTIM1/LPTIM2/QUADSPI/SAI2/TIM4/USART3 U14 PD13/FMC_A18/I2C1_SDA/I2C4_SDA/I2S3_MCK/LPTIM1_OUT/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/SAI2_SCK_A/TIM4_CH2 U13 PD14/FMC_D0/FMC_DA0/S\A\I\3\_\M\C\L\K\_\B\/TIM4_CH3/UART8_CTS 1E1 PD15/ADC1_EXTI15/ADC2_EXTI15/FMC_D1/FMC_DA1/LTDC_R1/SAI3_MCLK_A/TIM4_CH4/UART8_CTS 1C2
PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C2 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX 1A1 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK P1 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ 1A3 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 A10 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B7 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 B2 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX V7 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX U12 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS 1J4 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS V12 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 D2 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N C1 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 E3 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 1B2 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 D3 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX U10 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX W7 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS V8 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS V9 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ 1J7 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI W4 PE0/DCMI/FMC/I2S3/LPTIM1/LPTIM2/SAI2/SAI4/SPI3/TIM4/UART8 C2 PE1/DCMI_D3/F\M\C\_\N\B\L\1\/I2S2_MCK/LPTIM1_IN2/S\A\I\3\_\S\D\_\B\/UART8_TX 1A1 PE2/DEBUG_TRACECLK/ETH1_TXD3/FMC_A23/I2C4_SCL/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/SAI1_CK1/SAI1_MCLK_A/SPI4_SCK P1 PE3/DEBUG_TRACED0/FMC_A19/S\A\I\1\_\S\D\_\B\/SDMMC2_CK/T\I\M\1\5\_\B\K\I\N\ 1A3 PE4/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 A10 PE5/DCMI/DEBUG/DFSDM1/FMC/LTDC/SAI1/SDMMC1/SDMMC2/SPI4/TIM15 B7 PE6/DCMI/DEBUG/FMC/LTDC/SAI1/SAI2/SDMMC1/SDMMC2/SPI4/TIM15/TIM1 B2 PE7/DFSDM1_DATIN2/FMC_D4/FMC_DA4/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\0\/TIM1_ETR/TIM3_ETR/UART7_RX V7 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/TIM1_CH1N/UART7_TX U12 PE9/DAC1_EXTI9/DFSDM1_CKOUT/FMC_D6/FMC_DA6/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/TIM1_CH1/UART7_DE/UART7_RTS 1J4 PE10/DFSDM1_DATIN4/FMC_D7/FMC_DA7/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/TIM1_CH2N/UART7_CTS V12 PE11/ADC1/ADC2/DCMI/DFSDM1/FMC/LTDC/SAI2/SPI4/TIM1/USART6 D2 PE12/DFSDM1_DATIN5/FMC_D9/FMC_DA9/L\T\D\C\_\B\4\/S\A\I\2\_\S\C\K\_\B\/SDMMC1_D0DIR/SPI4_SCK/TIM1_CH3N C1 PE13/DCMI_D6/DFSDM1_CKIN5/FMC_D10/FMC_DA10/HDP_HDP2/LTDC_DE/S\A\I\2\_\F\S\_\B\/SPI4_MISO/TIM1_CH3 E3 PE14/FMC/LTDC/SAI2/SDMMC1/SPI4/TIM1/UART8 1B2 PE15/ADC1/ADC2/FMC/HDP/LTDC/TIM15/TIM1/UART8/USART2 D3 PF6/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/S\A\I\1\_\S\D\_\B\/S\A\I\4\_\S\C\K\_\B\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX U10 PF7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\A\I\1\_\M\C\L\K\_\B\/SPI5_SCK/TIM17_CH1/UART7_TX W7 PF8/DEBUG_TRACED12/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/S\A\I\1\_\S\C\K\_\B\/SPI5_MISO/TIM13_CH1/TIM16_CH1N/UART7_DE/UART7_RTS V8 PF9/DAC1_EXTI9/DEBUG_TRACED13/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/S\A\I\1\_\F\S\_\B\/SPI5_MOSI/TIM14_CH1/TIM17_CH1N/UART7_CTS V9 PF10/DCMI_D11/LTDC_DE/QUADSPI_CLK/SAI1_D3/SAI1_D4/SAI4_D3/SAI4_D4/T\I\M\1\6\_\B\K\I\N\ 1J7 PF11/ADC1_EXTI11/ADC1_INP2/ADC2_EXTI11/DCMI_D12/LTDC_G5/S\A\I\2\_\S\D\_\B\/SPI5_MOSI W4
PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ B5 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 V11 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 V6 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 W8 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS U7 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 U6 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 D1 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 R3 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 R2 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 B1 PH0-OSC_IN/RCC_OSC_IN H2 PH1-OSC_OUT/RCC_OSC_OUT J2 PG6/DCMI_D12/DEBUG_TRACED14/LTDC_R7/SDMMC2_CMD/T\I\M\1\7\_\B\K\I\N\ B5 PG7/DCMI/DEBUG/LTDC/QUADSPI/SAI1/UART8/USART6 V11 PG8/DEBUG/ETH1/LTDC/SAI4/SPDIFRX/SPI6/TIM2/TIM8/USART3/USART6 V6 PG9/DAC1/DCMI/DEBUG/FMC/LTDC/QUADSPI/SAI2/SPDIFRX/USART6 W8 PG10/DCMI_D2/DEBUG_TRACED10/F\M\C\_\N\E\3\/L\T\D\C\_\B\2\/LTDC_G3/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\2\/S\A\I\2\_\S\D\_\B\/UART8_CTS U7 PG11/ADC1/ADC2/DCMI/DEBUG/ETH1/LTDC/SPDIFRX/UART4/USART1 U6 PG12/ETH1/FMC/LPTIM1/LTDC/SAI4/SPDIFRX/SPI6/USART6 D1 PG13/DEBUG/ETH1/FMC/LPTIM1/LTDC/SAI1/SAI4/SPI6/USART6 R3 PG14/DEBUG/ETH1/FMC/LPTIM1/LTDC/QUADSPI/SAI4/SPI6/USART6 R2 PG15/ADC1/ADC2/DCMI/DEBUG/I2C2/SAI1/SDMMC3/USART6 B1 PH0-OSC_IN/RCC_OSC_IN H2 PH1-OSC_OUT/RCC_OSC_OUT J2
ST MICROELECTRONICS STM32MP153FADX TFBGA257
Part ID
ST MICROELECTRONICS STM32MP153FADX TFBGA257
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