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mirror of https://github.com/issus/altium-library.git synced 2025-04-02 11:36:56 +00:00

Create SCH - MCU - TI - TI MSPM0G110X VQFN-48 RGZ.SchLib

This commit is contained in:
Mark 2024-10-04 19:40:28 +01:00
parent 88c7bc0902
commit b0498fab80

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TI MSPM0G110X VQFN-48 RGZ
*
PA0/PA0/UART0.TX/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMG8.CCP1/SYSCTL.FCC_IN 1 PA1/PA1/UART0.RX/I2C0.SCL/TIMA0.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG8.IDX/TIMG8.CCP0 2 PA2/PA2/TIMG8.CCP1/SPI0.CS0/TIMG7.CCP1/SPI1.CS0/SYSCTL.ROSC 8 PA3/PA3/TIMG8.CCP0/SPI0.CS1_POCI1/UART2.CTS/TIMA0.CCP2/TIMG7.CCP0/TIMA0.CCP1/I2C1.SDA/SYSCTL.LFXIN 9 PA4/PA4/TIMG8.CCP1/SPI0.POCI/UART2.RTS/TIMA0.CCP3/SYSCTL.LFCLKIN/TIMG7.CCP1/I2C1.SCL/SYSCTL.LFXOUT 10 PA5/PA5/TIMG8.CCP0/SPI0.PICO/TIMA0.FAULT1/TIMA1.FAULT1/TIMG0.CCP0/TIMG6.CCP0/SYSCTL.HFXIN/FCC 11 PA6/PA6/TIMG8.CCP1/SPI0.SCLK/TIMA0.FAULT0/TIMA1.FAULT0/TIMG0.CCP1/SYSCTL.HFCLKIN/TIMG6.CCP1 12 PA7/PA7/SYSCTL.CLK_OUT/TIMG8.CCP0/TIMA0.CCP2/TIMG8.IDX/TIMG7.CCP1/TIMA0.CCP1 13 PA8/PA8/UART1.TX/SPI0.CS0/UART0.RTS/TIMA0.CCP0/TIMA1.CCP0_CMPL 16 PA9/PA9/UART1.RX/SPI0.PICO/UART0.CTS/TIMA0.CCP1/RTC/CCP0/CCP1/CLK 17 PA10/PA10/UART0.TX/SPI0.POCI/I2C0.SDA/TIMA1.CCP0/TIMG12.CCP0/TIMA0.CCP2/I2C1.SDA/SYSCTL.CLK_OUT 18 PA11/PA11/UART0.RX/SPI0.SCLK/I2C0.SCL/TIMA1.CCP1/TIMA0.CCP2_CMPL/I2C1.SCL 19 PA12/PA12/UART3.CTS/SPI0.SCLK/TIMG0.CCP0/TIMA0.CCP3/SYSCTL.FCC_IN 27 PA13/PA13/UART3.RTS/SPI0.POCI/UART3.RX/TIMG0.CCP1/TIMA0.CCP3_CMPL 28 PA14/PA14/UART0.CTS/SPI0.PICO/UART3.TX/TIMG12.CCP0/SYSCTL.CLK_OUT/ADC0.12 29 PA15/PA15/UART0.RTS/SPI1.CS2_POCI2/I2C1.SCL/TIMA1.CCP0/TIMG8.IDX/TIMA1.CCP0_CMPL/TIMA0.CCP2/ADC1.0 30 PA16/PA16/SPI1.POCI/I2C1.SDA/TIMA1.CCP1/TIMA1.CCP1_CMPL/TIMA0.CCP2_CMPL/SYSCTL.FCC_IN/ADC1.1 31 PA17/PA17/UART1.TX/SPI1.SCLK/I2C1.SCL/TIMA0.CCP3/TIMG7.CCP0/TIMA1.CCP0/ADC1.2 32 PA18/PA18/UART1.RX/SPI1.PICO/I2C1.SDA/TIMA0.CCP3_CMPL/TIMG7.CCP1/TIMA1.CCP1/ADC1.3/GPAMP.IN- 33 PA19/PA19/DEBUGSS.SWDIO 34 PA20/PA20/DEBUGSS.SWCLK 35 PA21/PA21/UART2.TX/TIMG8.CCP0/UART1.CTS/TIMA0.CCP0/TIMG6.CCP0/ADC1.7/ADC0.8/VREF.VREF- 39 PA22/PA22/UART2.RX/TIMG8.CCP1/UART1.RTS/TIMA0.CCP1/TIMG6.CCP1/ADC0.7/ADC1.8/GPAMP.OUT/CLK/CCP0 40 PA23/PA23/UART2.TX/TIMA0.CCP3/TIMG0.CCP0/UART3.CTS/TIMG7.CCP0/TIMG8.CCP0/VREF.VREF+/CS3 43 PA24/PA24/UART2.RX/SPI0.CS2_POCI2/TIMA0.CCP3_CMPL/TIMG0.CCP1/UART3.RTS/TIMG7.CCP1/TIMA1.CCP1/ADC0.3 44 PA25/PA25/UART3.RX/SPI1.CS3_CD_POCI3/TIMG12.CCP1/TIMA0.CCP3/TIMA0.CCP1_CMPL/ADC0.2 45 PA26/PA26/UART3.TX/SPI1.CS0/TIMG8.CCP0/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/ADC0.1/GPAMP.IN+ 46 PA27/PA27/RTC.RTC_OUT/SPI1.CS1_POCI1/TIMG8.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG7.CCP1/ADC0.0 47 PA28/PA28/UART0.TX/I2C0.SDA/TIMA0.CCP3/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/TIMA1.CCP0 3 PA31/PA31/UART0.RX/I2C0.SCL/TIMA0.CCP3_CMPL/TIMG12.CCP1/SYSCTL.CLK_OUT/TIMG7.CCP1/TIMA1.CCP1 5 VDD 6 VCORE 48 NRST/SYSCTL.NRST 4 VSS 7 VSS 49 PA0/PA0/UART0.TX/I2C0.SDA/TIMA0.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMG8.CCP1/SYSCTL.FCC_IN 1 PA1/PA1/UART0.RX/I2C0.SCL/TIMA0.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG8.IDX/TIMG8.CCP0 2 PA2/PA2/TIMG8.CCP1/SPI0.CS0/TIMG7.CCP1/SPI1.CS0/SYSCTL.ROSC 8 PA3/PA3/TIMG8.CCP0/SPI0.CS1_POCI1/UART2.CTS/TIMA0.CCP2/TIMG7.CCP0/TIMA0.CCP1/I2C1.SDA/SYSCTL.LFXIN 9 PA4/PA4/TIMG8.CCP1/SPI0.POCI/UART2.RTS/TIMA0.CCP3/SYSCTL.LFCLKIN/TIMG7.CCP1/I2C1.SCL/SYSCTL.LFXOUT 10 PA5/PA5/TIMG8.CCP0/SPI0.PICO/TIMA0.FAULT1/TIMA1.FAULT1/TIMG0.CCP0/TIMG6.CCP0/SYSCTL.HFXIN/FCC 11 PA6/PA6/TIMG8.CCP1/SPI0.SCLK/TIMA0.FAULT0/TIMA1.FAULT0/TIMG0.CCP1/SYSCTL.HFCLKIN/TIMG6.CCP1 12 PA7/PA7/SYSCTL.CLK_OUT/TIMG8.CCP0/TIMA0.CCP2/TIMG8.IDX/TIMG7.CCP1/TIMA0.CCP1 13 PA8/PA8/UART1.TX/SPI0.CS0/UART0.RTS/TIMA0.CCP0/TIMA1.CCP0_CMPL 16 PA9/PA9/UART1.RX/SPI0.PICO/UART0.CTS/TIMA0.CCP1/RTC/CCP0/CCP1/CLK 17 PA10/PA10/UART0.TX/SPI0.POCI/I2C0.SDA/TIMA1.CCP0/TIMG12.CCP0/TIMA0.CCP2/I2C1.SDA/SYSCTL.CLK_OUT 18 PA11/PA11/UART0.RX/SPI0.SCLK/I2C0.SCL/TIMA1.CCP1/TIMA0.CCP2_CMPL/I2C1.SCL 19 PA12/PA12/UART3.CTS/SPI0.SCLK/TIMG0.CCP0/TIMA0.CCP3/SYSCTL.FCC_IN 27 PA13/PA13/UART3.RTS/SPI0.POCI/UART3.RX/TIMG0.CCP1/TIMA0.CCP3_CMPL 28 PA14/PA14/UART0.CTS/SPI0.PICO/UART3.TX/TIMG12.CCP0/SYSCTL.CLK_OUT/ADC0.12 29 PA15/PA15/UART0.RTS/SPI1.CS2_POCI2/I2C1.SCL/TIMA1.CCP0/TIMG8.IDX/TIMA1.CCP0_CMPL/TIMA0.CCP2/ADC1.0 30 PA16/PA16/SPI1.POCI/I2C1.SDA/TIMA1.CCP1/TIMA1.CCP1_CMPL/TIMA0.CCP2_CMPL/SYSCTL.FCC_IN/ADC1.1 31 PA17/PA17/UART1.TX/SPI1.SCLK/I2C1.SCL/TIMA0.CCP3/TIMG7.CCP0/TIMA1.CCP0/ADC1.2 32 PA18/PA18/UART1.RX/SPI1.PICO/I2C1.SDA/TIMA0.CCP3_CMPL/TIMG7.CCP1/TIMA1.CCP1/ADC1.3/GPAMP.IN- 33 PA19/PA19/DEBUGSS.SWDIO 34 PA20/PA20/DEBUGSS.SWCLK 35 PA21/PA21/UART2.TX/TIMG8.CCP0/UART1.CTS/TIMA0.CCP0/TIMG6.CCP0/ADC1.7/ADC0.8/VREF.VREF- 39 PA22/PA22/UART2.RX/TIMG8.CCP1/UART1.RTS/TIMA0.CCP1/TIMG6.CCP1/ADC0.7/ADC1.8/GPAMP.OUT/CLK/CCP0 40 PA23/PA23/UART2.TX/TIMA0.CCP3/TIMG0.CCP0/UART3.CTS/TIMG7.CCP0/TIMG8.CCP0/VREF.VREF+/CS3 43 PA24/PA24/UART2.RX/SPI0.CS2_POCI2/TIMA0.CCP3_CMPL/TIMG0.CCP1/UART3.RTS/TIMG7.CCP1/TIMA1.CCP1/ADC0.3 44 PA25/PA25/UART3.RX/SPI1.CS3_CD_POCI3/TIMG12.CCP1/TIMA0.CCP3/TIMA0.CCP1_CMPL/ADC0.2 45 PA26/PA26/UART3.TX/SPI1.CS0/TIMG8.CCP0/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/ADC0.1/GPAMP.IN+ 46 PA27/PA27/RTC.RTC_OUT/SPI1.CS1_POCI1/TIMG8.CCP1/TIMA0.FAULT2/TIMA1.FAULT2/TIMG7.CCP1/ADC0.0 47 PA28/PA28/UART0.TX/I2C0.SDA/TIMA0.CCP3/TIMA0.FAULT0/TIMA1.FAULT0/TIMG7.CCP0/TIMA1.CCP0 3 PA31/PA31/UART0.RX/I2C0.SCL/TIMA0.CCP3_CMPL/TIMG12.CCP1/SYSCTL.CLK_OUT/TIMG7.CCP1/TIMA1.CCP1 5 VDD 6 VCORE 48 NRST/SYSCTL.NRST 4 VSS 7 VSS 49
PB2/PB2/UART3.TX/UART2.CTS/I2C1.SCL/TIMA0.CCP3/UART1.CTS/TIMG6.CCP0/TIMA1.CCP0 14 PB3/PB3/UART3.RX/UART2.RTS/I2C1.SDA/TIMA0.CCP3_CMPL/UART1.RTS/TIMG6.CCP1/TIMA1.CCP1 15 PB6/PB6/UART1.TX/SPI1.CS0/SPI0.CS1_POCI1/TIMG8.CCP0/UART2.CTS/TIMG6.CCP0/TIMA1.CCP0_CMPL 20 PB7/PB7/UART1.RX/SPI1.POCI/SPI0.CS2_POCI2/TIMG8.CCP1/UART2.RTS/TIMG6.CCP1/TIMA1.CCP1_CMPL 21 PB8/PB8/UART1.CTS/SPI1.PICO/TIMA0.CCP0 22 PB9/PB9/UART1.RTS/SPI1.SCLK/TIMA0.CCP1/TIMA0.CCP0_CMPL 23 PB14/PB14/SPI1.CS3_CD_POCI3/SPI1.POCI/SPI0.CS3_CD_POCI3/TIMG12.CCP1/TIMG8.IDX/TIMA0.CCP0 24 PB15/PB15/UART2.TX/SPI1.PICO/UART3.CTS/TIMG8.CCP0/TIMG7.CCP0 25 PB16/PB16/UART2.RX/SPI1.SCLK/UART3.RTS/TIMG8.CCP1/TIMG7.CCP1 26 PB17/PB17/UART2.TX/SPI0.PICO/SPI1.CS1_POCI1/TIMA1.CCP0/TIMA0.CCP2/ADC1.4 36 PB18/PB18/UART2.RX/SPI0.SCLK/SPI1.CS2_POCI2/TIMA1.CCP1/TIMA0.CCP2_CMPL/ADC1.5 37 PB19/PB19/SPI0.POCI/TIMG8.CCP1/UART0.CTS/TIMG7.CCP1/ADC1.6 38 PB20/PB20/SPI1.CS0/TIMA0.CCP2/TIMG12.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMA0.CCP1/ADC0.6/CS2/CCP1 41 PB24/PB24/TIMA0.CCP3/TIMG12.CCP1/ADC0.5/CS3/CS1/CCP1/CCP0 42 PB2/PB2/UART3.TX/UART2.CTS/I2C1.SCL/TIMA0.CCP3/UART1.CTS/TIMG6.CCP0/TIMA1.CCP0 14 PB3/PB3/UART3.RX/UART2.RTS/I2C1.SDA/TIMA0.CCP3_CMPL/UART1.RTS/TIMG6.CCP1/TIMA1.CCP1 15 PB6/PB6/UART1.TX/SPI1.CS0/SPI0.CS1_POCI1/TIMG8.CCP0/UART2.CTS/TIMG6.CCP0/TIMA1.CCP0_CMPL 20 PB7/PB7/UART1.RX/SPI1.POCI/SPI0.CS2_POCI2/TIMG8.CCP1/UART2.RTS/TIMG6.CCP1/TIMA1.CCP1_CMPL 21 PB8/PB8/UART1.CTS/SPI1.PICO/TIMA0.CCP0 22 PB9/PB9/UART1.RTS/SPI1.SCLK/TIMA0.CCP1/TIMA0.CCP0_CMPL 23 PB14/PB14/SPI1.CS3_CD_POCI3/SPI1.POCI/SPI0.CS3_CD_POCI3/TIMG12.CCP1/TIMG8.IDX/TIMA0.CCP0 24 PB15/PB15/UART2.TX/SPI1.PICO/UART3.CTS/TIMG8.CCP0/TIMG7.CCP0 25 PB16/PB16/UART2.RX/SPI1.SCLK/UART3.RTS/TIMG8.CCP1/TIMG7.CCP1 26 PB17/PB17/UART2.TX/SPI0.PICO/SPI1.CS1_POCI1/TIMA1.CCP0/TIMA0.CCP2/ADC1.4 36 PB18/PB18/UART2.RX/SPI0.SCLK/SPI1.CS2_POCI2/TIMA1.CCP1/TIMA0.CCP2_CMPL/ADC1.5 37 PB19/PB19/SPI0.POCI/TIMG8.CCP1/UART0.CTS/TIMG7.CCP1/ADC1.6 38 PB20/PB20/SPI1.CS0/TIMA0.CCP2/TIMG12.CCP0/TIMA0.FAULT1/TIMA1.FAULT1/TIMA0.CCP1/ADC0.6/CS2/CCP1 41 PB24/PB24/TIMA0.CCP3/TIMG12.CCP1/ADC0.5/CS3/CS1/CCP1/CCP0 42
TI MSPM0G110X VQFN-48 RGZ
Part ID
TI MSPM0G110X VQFN-48 RGZ
Comment
*
Attributes
Designator
IC?
Comment
*