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mirror of https://github.com/issus/altium-library.git synced 2025-04-02 03:36:35 +00:00

Create symbols/MCU - STM32/SCH - MCU - STM32 - ST MICROELECTRONICS STM32MP135DAEX LFBGA289.SchLib

This commit is contained in:
Mark 2023-06-27 04:06:00 +01:00
parent 4d0db56547
commit d5b75a02f2

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Name
Comment
Description
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ST MICROELECTRONICS STM32MP135DAEX LFBGA289
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VSS_USBHS N10 VSS_PLL2 P13 VSS_PLL J4 VSS_ANA M5 VSS A1 VSS A17 VSS C8 VSS D3 VSS D12 VSS E5 VSS F13 VSS F15 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS H7 VSS H11 VSS H14 VSS J7 VSS J9 VSS J11 VSS K3 VSS K7 VSS K11 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS M15 VSS N4 VSS P11 VSS R5 VSS R8 VSS U1 VSS U17 VSSA N7 VDDSD2 D11 VDDSD1 C12 VDDQ_DDR E12 VDDQ_DDR F12 VDDQ_DDR G12 VDDQ_DDR H12 VDDQ_DDR J12 VDDQ_DDR K12 VDDQ_DDR L12 VDDQ_DDR M12 VDDQ_DDR N12 VDDCPU F6 VDDCPU F8 VDDCPU F9 VDDCPU H6 VDDCPU J6 VDDCORE H8 VDDCORE H9 VDDCORE H10 VDDCORE J8 VDDCORE J10 VDDCORE J13 VDDCORE K8 VDDCORE K9 VDDCORE K10 VDD3V3_USBHS P10 VDD_PLL2 R13 VDD_PLL J5 VDD_ANA M4 VDD F7 VDD F10 VDD F11 VDD G6 VDD K6 VDD L6 VDD M6 VDD M7 VDD M8 VDD M9 VDD M10 VDD M11 VDD R9 VDDA1V8_REG R11 VDDA1V1_REG N11 VDDA P7 VBAT J2 VREF+ R6 VREF- P6 PDR_ON T10 NRST U10 VSS_USBHS N10 VSS_PLL2 P13 VSS_PLL J4 VSS_ANA M5 VSS A1 VSS A17 VSS C8 VSS D3 VSS D12 VSS E5 VSS F13 VSS F15 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS H7 VSS H11 VSS H14 VSS J7 VSS J9 VSS J11 VSS K3 VSS K7 VSS K11 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS M15 VSS N4 VSS P11 VSS R5 VSS R8 VSS U1 VSS U17 VSSA N7 VDDSD2 D11 VDDSD1 C12 VDDQ_DDR E12 VDDQ_DDR F12 VDDQ_DDR G12 VDDQ_DDR H12 VDDQ_DDR J12 VDDQ_DDR K12 VDDQ_DDR L12 VDDQ_DDR M12 VDDQ_DDR N12 VDDCPU F6 VDDCPU F8 VDDCPU F9 VDDCPU H6 VDDCPU J6 VDDCORE H8 VDDCORE H9 VDDCORE H10 VDDCORE J8 VDDCORE J10 VDDCORE J13 VDDCORE K8 VDDCORE K9 VDDCORE K10 VDD3V3_USBHS P10 VDD_PLL2 R13 VDD_PLL J5 VDD_ANA M4 VDD F7 VDD F10 VDD F11 VDD G6 VDD K6 VDD L6 VDD M6 VDD M7 VDD M8 VDD M9 VDD M10 VDD M11 VDD R9 VDDA1V8_REG R11 VDDA1V1_REG N11 VDDA P7 VBAT J2 VREF+ R6 VREF- P6 PDR_ON T10 NRST U10
BYPASS_REG1V8 T14 DDR_A0/DDR_A0 G16 DDR_A1/DDR_A1 K15 DDR_A10/DDR_A10 J14 DDR_A11/DDR_A11 K13 DDR_A12/DDR_A12 K17 DDR_A13/DDR_A13 F14 DDR_A14/DDR_A14 L17 DDR_A15/DDR_A15 K16 DDR_A2/DDR_A2 F17 DDR_A3/DDR_A3 G15 DDR_A4/DDR_A4 M14 DDR_A5/DDR_A5 E16 DDR_A6/DDR_A6 M17 DDR_A7/DDR_A7 G14 DDR_A8/DDR_A8 L15 DDR_A9/DDR_A9 F16 DDR_ATO/DDR_ATO L13 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G17 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ L16 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ G13 DDR_CASN/DDR_CASN J15 DDR_CKE/DDR_CKE K14 DDR_CLKN/DDR_CLKN J17 DDR_CLKP/DDR_CLKP J16 DDR_CSN/DDR_CSN H16 DDR_DQ0/DDR_DQ0 B17 DDR_DQ1/DDR_DQ1 C15 DDR_DQ10/DDR_DQ10 N15 DDR_DQ11/DDR_DQ11 P15 DDR_DQ12/DDR_DQ12 R15 DDR_DQ13/DDR_DQ13 P16 DDR_DQ14/DDR_DQ14 T17 DDR_DQ15/DDR_DQ15 T16 DDR_DQ2/DDR_DQ2 E13 DDR_DQ3/DDR_DQ3 D17 DDR_DQ4/DDR_DQ4 B16 DDR_DQ5/DDR_DQ5 D16 DDR_DQ6/DDR_DQ6 E14 DDR_DQ7/DDR_DQ7 E15 DDR_DQ8/DDR_DQ8 N16 DDR_DQ9/DDR_DQ9 P17 DDR_DQM0/DDR_DQM0 D15 DDR_DQM1/DDR_DQM1 N14 DDR_DQS0N/DDR_DQS0N C16 DDR_DQS0P/DDR_DQS0P C17 DDR_DQS1N/DDR_DQS1N R16 DDR_DQS1P/DDR_DQS1P R17 DDR_DTO0/DDR_DTO0 L14 DDR_DTO1/DDR_DTO1 M16 DDR_ODT/DDR_ODT H15 DDR_RASN/DDR_RASN H17 DDR_RESETN/DDR_RESETN E17 DDR_VREF/DDR_VREF M13 DDR_WEN/DDR_WEN H13 DDR_ZQ/DDR_ZQ N17 NJTRST/DEBUG_JTRST N9 PWR_CPU_ON R3 PWR_LP N13 PWR_ON P14 USB_DM1/USBH_HS1_DM U13 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM U11 USB_DP1/USBH_HS1_DP T13 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP T11 USB_RREF U12 BYPASS_REG1V8 T14 DDR_A0/DDR_A0 G16 DDR_A1/DDR_A1 K15 DDR_A10/DDR_A10 J14 DDR_A11/DDR_A11 K13 DDR_A12/DDR_A12 K17 DDR_A13/DDR_A13 F14 DDR_A14/DDR_A14 L17 DDR_A15/DDR_A15 K16 DDR_A2/DDR_A2 F17 DDR_A3/DDR_A3 G15 DDR_A4/DDR_A4 M14 DDR_A5/DDR_A5 E16 DDR_A6/DDR_A6 M17 DDR_A7/DDR_A7 G14 DDR_A8/DDR_A8 L15 DDR_A9/DDR_A9 F16 DDR_ATO/DDR_ATO L13 D\D\R\_\B\A\0\/D\D\R\_\B\A\0\ G17 D\D\R\_\B\A\1\/D\D\R\_\B\A\1\ L16 D\D\R\_\B\A\2\/D\D\R\_\B\A\2\ G13 DDR_CASN/DDR_CASN J15 DDR_CKE/DDR_CKE K14 DDR_CLKN/DDR_CLKN J17 DDR_CLKP/DDR_CLKP J16 DDR_CSN/DDR_CSN H16 DDR_DQ0/DDR_DQ0 B17 DDR_DQ1/DDR_DQ1 C15 DDR_DQ10/DDR_DQ10 N15 DDR_DQ11/DDR_DQ11 P15 DDR_DQ12/DDR_DQ12 R15 DDR_DQ13/DDR_DQ13 P16 DDR_DQ14/DDR_DQ14 T17 DDR_DQ15/DDR_DQ15 T16 DDR_DQ2/DDR_DQ2 E13 DDR_DQ3/DDR_DQ3 D17 DDR_DQ4/DDR_DQ4 B16 DDR_DQ5/DDR_DQ5 D16 DDR_DQ6/DDR_DQ6 E14 DDR_DQ7/DDR_DQ7 E15 DDR_DQ8/DDR_DQ8 N16 DDR_DQ9/DDR_DQ9 P17 DDR_DQM0/DDR_DQM0 D15 DDR_DQM1/DDR_DQM1 N14 DDR_DQS0N/DDR_DQS0N C16 DDR_DQS0P/DDR_DQS0P C17 DDR_DQS1N/DDR_DQS1N R16 DDR_DQS1P/DDR_DQS1P R17 DDR_DTO0/DDR_DTO0 L14 DDR_DTO1/DDR_DTO1 M16 DDR_ODT/DDR_ODT H15 DDR_RASN/DDR_RASN H17 DDR_RESETN/DDR_RESETN E17 DDR_VREF/DDR_VREF M13 DDR_WEN/DDR_WEN H13 DDR_ZQ/DDR_ZQ N17 NJTRST/DEBUG_JTRST N9 PWR_CPU_ON R3 PWR_LP N13 PWR_ON P14 USB_DM1/USBH_HS1_DM U13 USB_DM2/USBH_HS2_DM/USB_OTG_HS_DM U11 USB_DP1/USBH_HS1_DP T13 USB_DP2/USBH_HS2_DP/USB_OTG_HS_DP T11 USB_RREF U12
PA0/ADC1/ADC2/ETH1/ETH2/SAI1/TIM15/TIM2/TIM5/TIM8/UART5 U3 PA1/ADC1/ADC2/DFSDM1/ETH1/LPTIM3/TIM15/TIM2/TIM5/USART2 R4 PA2/ADC1_INP1/ADC2_INP1/ETH1_MDIO/LPTIM4_OUT/TIM15_CH1/TIM2_CH3/TIM5_CH3/USART2_TX P5 PA3/ADC1/ETH1/ETH2/I2S1/LPTIM5/PWR/SAI1/SPI1/TIM15/TIM2/TIM5/USART2 N8 PA4/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM5/USART2 U5 PA5/ADC1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM2/TIM8/USART2 U4 PA6/ADC1/I2S1/SAI2/SPI1/TAMP/TIM13/TIM1/TIM3/TIM8/UART4/USART1 T8 PA7/ADC1/ETH1/I2S1/SAI2/SPI1/TIM14/TIM1/TIM3/TIM8/USART1 U2 PA8/ETH2/FMC/I2C4/I2S2/LTDC/RCC/SAI2/SPI2/SPI5/TIM8/USART1/USB M2 PA9/DCMIPP_D0/DFSDM1_DATIN0/F\M\C\_\N\W\A\I\T\/I2C3_SMBA/LTDC_R6/TIM1_CH2/UART4_TX/USART1_TX A2 PA10/TIM1_CH3/USB_OTG_HS_ID U15 PA11/ADC1/ADC2/ETH1/ETH2/I2C5/I2S2/SPI2/TIM1/USART1 T2 PA12/DCMIPP/ETH2/FMC/LTDC/SAI2/TIM1/USART1 E3 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX P3 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2/USB_OTG_HS_SOF T12 PA15/ADC1/ADC2/DCMIPP/DEBUG/FMC/HDP/I2S4/LTDC/TIM2/UART4 E6 PA0/ADC1/ADC2/ETH1/ETH2/SAI1/TIM15/TIM2/TIM5/TIM8/UART5 U3 PA1/ADC1/ADC2/DFSDM1/ETH1/LPTIM3/TIM15/TIM2/TIM5/USART2 R4 PA2/ADC1_INP1/ADC2_INP1/ETH1_MDIO/LPTIM4_OUT/TIM15_CH1/TIM2_CH3/TIM5_CH3/USART2_TX P5 PA3/ADC1/ETH1/ETH2/I2S1/LPTIM5/PWR/SAI1/SPI1/TIM15/TIM2/TIM5/USART2 N8 PA4/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM5/USART2 U5 PA5/ADC1/ETH1/ETH2/I2S1/SAI1/SPI1/TIM2/TIM8/USART2 U4 PA6/ADC1/I2S1/SAI2/SPI1/TAMP/TIM13/TIM1/TIM3/TIM8/UART4/USART1 T8 PA7/ADC1/ETH1/I2S1/SAI2/SPI1/TIM14/TIM1/TIM3/TIM8/USART1 U2 PA8/ETH2/FMC/I2C4/I2S2/LTDC/RCC/SAI2/SPI2/SPI5/TIM8/USART1/USB M2 PA9/DCMIPP_D0/DFSDM1_DATIN0/F\M\C\_\N\W\A\I\T\/I2C3_SMBA/LTDC_R6/TIM1_CH2/UART4_TX/USART1_TX A2 PA10/TIM1_CH3/USB_OTG_HS_ID U15 PA11/ADC1/ADC2/ETH1/ETH2/I2C5/I2S2/SPI2/TIM1/USART1 T2 PA12/DCMIPP/ETH2/FMC/LTDC/SAI2/TIM1/USART1 E3 PA13/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_1/UART4_TX P3 PA14/DEBUG_DBTRGI/DEBUG_DBTRGO/RCC_MCO_2/USB_OTG_HS_SOF T12 PA15/ADC1/ADC2/DCMIPP/DEBUG/FMC/HDP/I2S4/LTDC/TIM2/UART4 E6
PB0/ADC1/ADC2/DEBUG/ETH1/I2S1/SAI2/TIM1/TIM3/TIM8/UART4/USART1 U7 PB1/ADC1/ADC2/DFSDM1/ETH1/I2S1/SPI1/TIM1/TIM3/TIM8/UART4 T7 PB2/ETH2/FMC/I2S/LTDC/QUADSPI/RTC/SAI1/TAMP/UART4 H4 PB3/DEBUG/I2S4/LTDC/SAI2/SDMMC1/SDMMC2/SPI4/TIM2/UART7 C11 PB4/DEBUG/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM16/TIM3/USART3 B13 PB5/DEBUG/FDCAN2/I2C4/I2S2/LTDC/SDMMC1/SPI2/TIM17/TIM3/UART5 C10 PB6/DCMIPP/DEBUG/ETH2/FMC/HDP/LTDC/QUADSPI/SAI1/TIM16/TIM4/TIM8/USART1 C1 PB7/DCMIPP_D13/DCMIPP_PIXCLK/F\M\C\_\N\C\E\2\/F\M\C\_\N\L\/I2C4_SDA/I2S4_CK/TIM17_CH1N/TIM4_CH2 A4 PB8/DCMIPP_D6/DFSDM1_DATIN1/FMC_D13/FMC_DA13/I2C1_SCL/I2C3_SCL/SAI1_D1/TIM16_CH1/TIM4_CH3/UART4_RX D1 PB9/DEBUG_TRACED3/FDCAN1_TX/I2C4_SDA/L\T\D\C\_\B\1\/LTDC_DE/SDMMC1_CDIR/SDMMC2_D5/TIM4_CH4/UART5_TX A12 PB10/I2C5_SMBA/I2S2_CK/I2S4_WS/LPTIM2_IN1/LTDC_R3/SPI2_SCK/S\P\I\4\_\N\S\S\/TIM2_CH3/USART3_TX D10 PB11/ADC1_EXTI11/ADC2_EXTI11/ETH1_TX_CTL/ETH1_TX_EN/I2C5_SMBA/LPTIM1_OUT/TIM2_CH4/USART3_RX N5 PB12/DEBUG/DFSDM1/I2C2/LTDC/SDMMC1/UART5/UART7/USART3 D9 PB13/DEBUG/FDCAN2/I2C4/I2S2/LPTIM2/LTDC/SDMMC1/SPI2/TIM1/UART5 E10 PB14/DEBUG_TRACED0/LTDC_G5/LTDC_R0/SDMMC1_D4/SDMMC2_D0/TIM12_CH1/TIM1_CH2N/TIM8_CH2N/USART1_TX A13 PB15/ADC1/ADC2/DFSDM1/I2S4/LTDC/RTC/SAI2/SDMMC1/SDMMC2/SPI4/TIM12/TIM1/TIM8/UART7 B12 PB0/ADC1/ADC2/DEBUG/ETH1/I2S1/SAI2/TIM1/TIM3/TIM8/UART4/USART1 U7 PB1/ADC1/ADC2/DFSDM1/ETH1/I2S1/SPI1/TIM1/TIM3/TIM8/UART4 T7 PB2/ETH2/FMC/I2S/LTDC/QUADSPI/RTC/SAI1/TAMP/UART4 H4 PB3/DEBUG/I2S4/LTDC/SAI2/SDMMC1/SDMMC2/SPI4/TIM2/UART7 C11 PB4/DEBUG/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM16/TIM3/USART3 B13 PB5/DEBUG/FDCAN2/I2C4/I2S2/LTDC/SDMMC1/SPI2/TIM17/TIM3/UART5 C10 PB6/DCMIPP/DEBUG/ETH2/FMC/HDP/LTDC/QUADSPI/SAI1/TIM16/TIM4/TIM8/USART1 C1 PB7/DCMIPP_D13/DCMIPP_PIXCLK/F\M\C\_\N\C\E\2\/F\M\C\_\N\L\/I2C4_SDA/I2S4_CK/TIM17_CH1N/TIM4_CH2 A4 PB8/DCMIPP_D6/DFSDM1_DATIN1/FMC_D13/FMC_DA13/I2C1_SCL/I2C3_SCL/SAI1_D1/TIM16_CH1/TIM4_CH3/UART4_RX D1 PB9/DEBUG_TRACED3/FDCAN1_TX/I2C4_SDA/L\T\D\C\_\B\1\/LTDC_DE/SDMMC1_CDIR/SDMMC2_D5/TIM4_CH4/UART5_TX A12 PB10/I2C5_SMBA/I2S2_CK/I2S4_WS/LPTIM2_IN1/LTDC_R3/SPI2_SCK/S\P\I\4\_\N\S\S\/TIM2_CH3/USART3_TX D10 PB11/ADC1_EXTI11/ADC2_EXTI11/ETH1_TX_CTL/ETH1_TX_EN/I2C5_SMBA/LPTIM1_OUT/TIM2_CH4/USART3_RX N5 PB12/DEBUG/DFSDM1/I2C2/LTDC/SDMMC1/UART5/UART7/USART3 D9 PB13/DEBUG/FDCAN2/I2C4/I2S2/LPTIM2/LTDC/SDMMC1/SPI2/TIM1/UART5 E10 PB14/DEBUG_TRACED0/LTDC_G5/LTDC_R0/SDMMC1_D4/SDMMC2_D0/TIM12_CH1/TIM1_CH2N/TIM8_CH2N/USART1_TX A13 PB15/ADC1/ADC2/DFSDM1/I2S4/LTDC/RTC/SAI2/SDMMC1/SDMMC2/SPI4/TIM12/TIM1/TIM8/UART7 B12
PC0/ADC1/ADC2/I2S1/SAI1/SPI1/TAMP/USART1 T3 PC1/ADC2_INP2/DFSDM1_DATIN0/ETH1_CRS_DV/ETH1_GTX_CLK/ETH1_RX_DV/SAI1_D3 U8 PC2/ADC1_INP15/ETH1_TXD2/I2S1_WS/SAI2_CK1/SAI2_MCLK_A/S\P\I\1\_\N\S\S\/S\P\I\5\_\N\S\S\/USART1_DE/USART1_RTS U9 PC3/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TAMP/UART5 T5 PC4/ADC1/ADC2/DFSDM1/ETH1/I2S1/SAI1/SAI2/SPDIFRX/TIM3/UART5 U6 PC5/ADC1/ADC2/DFSDM1/ETH1/I2S/SAI1/SAI2/SPDIFRX/USART2 R7 PC6/DEBUG/DFSDM1/FMC/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 B11 PC7/DEBUG/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART3/USART6 A11 PC8/DEBUG/I2S3/LTDC/SAI2/SDMMC1/SPI3/TIM3/TIM8/UART5/USART3/USART6 D14 PC9/DEBUG_TRACED1/FDCAN1_TX/L\T\D\C\_\B\4\/SDMMC1_D1/TIM3_CH4/TIM8_CH4/UART5_CTS/USART3_RTS A16 PC10/DEBUG_TRACED2/I2C1_SCL/I2S3_CK/S\A\I\2\_\M\C\L\K\_\B\/SDMMC1_D2/SPI3_SCK/USART3_TX B14 PC11/ADC1/ADC2/DEBUG/I2C1/I2S3/SAI2/SDMMC1/SPI3/UART5/USART3 C14 PC12/DEBUG_TRACECLK/LTDC_DE/S\A\I\2\_\S\D\_\B\/SDMMC1_CK/UART7_TX B15 PC13/PWR_WKUP3/RTC_LSCO/RTC_LSCO_OUT1/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2 K4 PC14-OSC32_IN/RCC_OSC32_IN K1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT K2 PC0/ADC1/ADC2/I2S1/SAI1/SPI1/TAMP/USART1 T3 PC1/ADC2_INP2/DFSDM1_DATIN0/ETH1_CRS_DV/ETH1_GTX_CLK/ETH1_RX_DV/SAI1_D3 U8 PC2/ADC1_INP15/ETH1_TXD2/I2S1_WS/SAI2_CK1/SAI2_MCLK_A/S\P\I\1\_\N\S\S\/S\P\I\5\_\N\S\S\/USART1_DE/USART1_RTS U9 PC3/ADC1/DFSDM1/ETH1/ETH2/I2S1/SAI1/SPI1/TAMP/UART5 T5 PC4/ADC1/ADC2/DFSDM1/ETH1/I2S1/SAI1/SAI2/SPDIFRX/TIM3/UART5 U6 PC5/ADC1/ADC2/DFSDM1/ETH1/I2S/SAI1/SAI2/SPDIFRX/USART2 R7 PC6/DEBUG/DFSDM1/FMC/HDP/I2S3/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART6 B11 PC7/DEBUG/HDP/I2S2/LTDC/SDMMC1/SDMMC2/TIM3/TIM8/USART3/USART6 A11 PC8/DEBUG/I2S3/LTDC/SAI2/SDMMC1/SPI3/TIM3/TIM8/UART5/USART3/USART6 D14 PC9/DEBUG_TRACED1/FDCAN1_TX/L\T\D\C\_\B\4\/SDMMC1_D1/TIM3_CH4/TIM8_CH4/UART5_CTS/USART3_RTS A16 PC10/DEBUG_TRACED2/I2C1_SCL/I2S3_CK/S\A\I\2\_\M\C\L\K\_\B\/SDMMC1_D2/SPI3_SCK/USART3_TX B14 PC11/ADC1/ADC2/DEBUG/I2C1/I2S3/SAI2/SDMMC1/SPI3/UART5/USART3 C14 PC12/DEBUG_TRACECLK/LTDC_DE/S\A\I\2\_\S\D\_\B\/SDMMC1_CK/UART7_TX B15 PC13/PWR_WKUP3/RTC_LSCO/RTC_LSCO_OUT1/RTC_OUT1/RTC_TS/TAMP_IN1/TAMP_OUT2 K4 PC14-OSC32_IN/RCC_OSC32_IN K1 PC15-OSC32_OUT/ADC1_EXTI15/ADC2_EXTI15/RCC_OSC32_OUT K2
PD0/DCMIPP_D1/FDCAN1_RX/FMC_D2/FMC_DA2/SAI1_CK1/SAI1_MCLK_A E4 PD1/DCMIPP_D13/FMC_D3/FMC_DA3/I2C5_SCL/I2S4_SDO/L\T\D\C\_\B\6\/LTDC_G2/Q\U\A\D\S\P\I\_\B\K\1\_\N\C\S\/SPI4_MOSI/UART4_TX D5 PD2/DEBUG_TRACED4/I2C1_SMBA/I2S3_WS/SAI2_D1/SDMMC1_CMD/S\P\I\3\_\N\S\S\/TIM3_ETR/USART3_RX A15 PD3/DCMIPP_D5/DFSDM1_CKOUT/FMC_CLK/I2C1_SDA/SAI1_D3/TIM2_CH1/TIM2_ETR/USART2_CTS/U\S\A\R\T\2\_\N\S\S\ B1 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/I2S3_SDI/LTDC_R1/LTDC_R4/LTDC_R6/QUADSPI_CLK/SPI3_MISO/USART2_DE/USART2_RTS E7 PD5/F\M\C\_\N\W\E\/L\T\D\C\_\B\0\/LTDC_G4/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\ A6 PD6/DCMIPP_D0/DCMIPP_D4/SAI1_D1/SAI1_SD_A/TIM16_CH1N/UART4_TX D2 PD7/ETH1/FMC/I2C2/I2C3/QUADSPI/RCC/SPDIFRX/USART2 N3 PD8/DCMIPP_D3/DCMIPP_D9/I2S4_WS/UART4_RX/USART2_TX/USART3_TX C5 PD9/DEBUG_TRACECLK/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/L\T\D\C\_\B\5\/LTDC_CLK/SDMMC2_CDIR E8 PD10/DCMIPP/FMC/I2C5/I2S4/LTDC/RTC/SPI4/USART3 A3 PD11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2C4/LPTIM2/LTDC/QUADSPI/SPDIFRX/UART7/USART3 E2 PD12/DCMIPP_D6/FMC_A17/FMC_ALE/I2C1_SCL/LPTIM1_IN1/TIM4_CH1/USART3_DE/USART3_RTS C6 PD13/FMC/LPTIM2/LTDC/QUADSPI/SAI1/TIM4/TIM8/USART1 J1 PD14/DCMIPP_D8/FMC_D0/FMC_DA0/I2C3_SDA/LTDC_R4/TIM4_CH3/UART8_CTS/USART1_RX B3 PD15/ADC1_EXTI15/ADC2_EXTI15/DFSDM1_DATIN2/FMC_D1/FMC_DA1/L\T\D\C\_\B\5\/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/TIM4_CH4/USART2_RX C7 PD0/DCMIPP_D1/FDCAN1_RX/FMC_D2/FMC_DA2/SAI1_CK1/SAI1_MCLK_A E4 PD1/DCMIPP_D13/FMC_D3/FMC_DA3/I2C5_SCL/I2S4_SDO/L\T\D\C\_\B\6\/LTDC_G2/Q\U\A\D\S\P\I\_\B\K\1\_\N\C\S\/SPI4_MOSI/UART4_TX D5 PD2/DEBUG_TRACED4/I2C1_SMBA/I2S3_WS/SAI2_D1/SDMMC1_CMD/S\P\I\3\_\N\S\S\/TIM3_ETR/USART3_RX A15 PD3/DCMIPP_D5/DFSDM1_CKOUT/FMC_CLK/I2C1_SDA/SAI1_D3/TIM2_CH1/TIM2_ETR/USART2_CTS/U\S\A\R\T\2\_\N\S\S\ B1 PD4/DFSDM1_CKIN0/F\M\C\_\N\O\E\/I2S3_SDI/LTDC_R1/LTDC_R4/LTDC_R6/QUADSPI_CLK/SPI3_MISO/USART2_DE/USART2_RTS E7 PD5/F\M\C\_\N\W\E\/L\T\D\C\_\B\0\/LTDC_G4/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\ A6 PD6/DCMIPP_D0/DCMIPP_D4/SAI1_D1/SAI1_SD_A/TIM16_CH1N/UART4_TX D2 PD7/ETH1/FMC/I2C2/I2C3/QUADSPI/RCC/SPDIFRX/USART2 N3 PD8/DCMIPP_D3/DCMIPP_D9/I2S4_WS/UART4_RX/USART2_TX/USART3_TX C5 PD9/DEBUG_TRACECLK/DFSDM1_DATIN3/FMC_D14/FMC_DA14/L\T\D\C\_\B\0\/L\T\D\C\_\B\5\/LTDC_CLK/SDMMC2_CDIR E8 PD10/DCMIPP/FMC/I2C5/I2S4/LTDC/RTC/SPI4/USART3 A3 PD11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2C4/LPTIM2/LTDC/QUADSPI/SPDIFRX/UART7/USART3 E2 PD12/DCMIPP_D6/FMC_A17/FMC_ALE/I2C1_SCL/LPTIM1_IN1/TIM4_CH1/USART3_DE/USART3_RTS C6 PD13/FMC/LPTIM2/LTDC/QUADSPI/SAI1/TIM4/TIM8/USART1 J1 PD14/DCMIPP_D8/FMC_D0/FMC_DA0/I2C3_SDA/LTDC_R4/TIM4_CH3/UART8_CTS/USART1_RX B3 PD15/ADC1_EXTI15/ADC2_EXTI15/DFSDM1_DATIN2/FMC_D1/FMC_DA1/L\T\D\C\_\B\5\/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/TIM4_CH4/USART2_RX C7
PE0/DCMIPP_D1/DCMIPP_D12/FDCAN2_RX/FMC_A11/L\T\D\C\_\B\1\/L\T\D\C\_\B\5\/UART8_RX D6 PE1/DCMIPP_D3/DCMIPP_D12/F\M\C\_\N\B\L\1\/LPTIM1_IN2/LTDC_HSYNC/LTDC_R4/UART8_TX B5 PE2/DEBUG/ETH2/FMC/I2C4/LTDC/SAI1/SPDIFRX/SPI5/TIM2/USART6 L1 PE3/DEBUG/FDCAN1/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM15/USART3 D13 PE4/DCMIPP/DFSDM1/FMC/I2S/LTDC/QUADSPI/SAI1/SPI5/TIM15/UART7/UART8 H5 PE5/ETH1_TXD3/F\M\C\_\N\E\1\/S\A\I\2\_\S\C\K\_\B\/TIM15_CH1/TIM8_CH3/UART4_RX T9 PE6/DCMIPP/ETH2/FMC/I2C3/LTDC/RCC/SAI1/SAI2/TIM15/TIM1/UART4 N1 PE7/FMC_D4/FMC_DA4/LPTIM2_IN1/L\T\D\C\_\B\3\/LTDC_R5/TIM1_ETR/UART5_TX A5 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/I2C1_SDA/TIM1_CH1N/UART7_TX A7 PE9/DCMIPP_D7/FMC_D6/FMC_DA6/HDP_HDP3/LTDC_HSYNC/LTDC_R7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/TIM1_CH1 B6 PE10/FDCAN1_TX/FMC_D7/FMC_DA7/TIM1_CH2N/UART7_RX B8 PE11/ADC1/ADC2/DCMIPP/ETH1/ETH2/FMC/I2S4/LTDC/SAI1/SPI4/TIM1/USART2/USART6 D4 PE12/DCMIPP/FMC/HDP/I2S4/LTDC/SPI4/TIM1/UART8 B4 PE13/DCMIPP_D4/FMC_D10/FMC_DA10/I2C5_SDA/I2S4_SDI/L\T\D\C\_\B\1\/LTDC_R6/SPI4_MISO/TIM1_CH3 C4 PE14/DCMIPP/FMC/LTDC/QUADSPI/SAI1/TAMP/TIM1/UART8 C3 PE15/ADC1/ADC2/DCMIPP/FMC/HDP/I2C4/LTDC/TIM1/TIM2/USART2 D8 PE0/DCMIPP_D1/DCMIPP_D12/FDCAN2_RX/FMC_A11/L\T\D\C\_\B\1\/L\T\D\C\_\B\5\/UART8_RX D6 PE1/DCMIPP_D3/DCMIPP_D12/F\M\C\_\N\B\L\1\/LPTIM1_IN2/LTDC_HSYNC/LTDC_R4/UART8_TX B5 PE2/DEBUG/ETH2/FMC/I2C4/LTDC/SAI1/SPDIFRX/SPI5/TIM2/USART6 L1 PE3/DEBUG/FDCAN1/I2S4/LTDC/SAI2/SDMMC2/SPI4/TIM15/USART3 D13 PE4/DCMIPP/DFSDM1/FMC/I2S/LTDC/QUADSPI/SAI1/SPI5/TIM15/UART7/UART8 H5 PE5/ETH1_TXD3/F\M\C\_\N\E\1\/S\A\I\2\_\S\C\K\_\B\/TIM15_CH1/TIM8_CH3/UART4_RX T9 PE6/DCMIPP/ETH2/FMC/I2C3/LTDC/RCC/SAI1/SAI2/TIM15/TIM1/UART4 N1 PE7/FMC_D4/FMC_DA4/LPTIM2_IN1/L\T\D\C\_\B\3\/LTDC_R5/TIM1_ETR/UART5_TX A5 PE8/DFSDM1_CKIN2/FMC_D5/FMC_DA5/I2C1_SDA/TIM1_CH1N/UART7_TX A7 PE9/DCMIPP_D7/FMC_D6/FMC_DA6/HDP_HDP3/LTDC_HSYNC/LTDC_R7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\1\/TIM1_CH1 B6 PE10/FDCAN1_TX/FMC_D7/FMC_DA7/TIM1_CH2N/UART7_RX B8 PE11/ADC1/ADC2/DCMIPP/ETH1/ETH2/FMC/I2S4/LTDC/SAI1/SPI4/TIM1/USART2/USART6 D4 PE12/DCMIPP/FMC/HDP/I2S4/LTDC/SPI4/TIM1/UART8 B4 PE13/DCMIPP_D4/FMC_D10/FMC_DA10/I2C5_SDA/I2S4_SDI/L\T\D\C\_\B\1\/LTDC_R6/SPI4_MISO/TIM1_CH3 C4 PE14/DCMIPP/FMC/LTDC/QUADSPI/SAI1/TAMP/TIM1/UART8 C3 PE15/ADC1/ADC2/DCMIPP/FMC/HDP/I2C4/LTDC/TIM1/TIM2/USART2 D8
PF0/DEBUG_TRACED13/DFSDM1_CKOUT/FMC_A0/LTDC_G0/LTDC_R6/SDMMC2_D4/USART3_CK C13 PF1/DEBUG_TRACED7/FMC_A1/HDP_HDP7/I2C2_SDA/I2S3_SDO/L\T\D\C\_\B\7\/LTDC_G1/SPI3_MOSI B9 PF2/DEBUG_TRACED1/DFSDM1_CKIN1/FMC_A2/I2C2_SCL/L\T\D\C\_\B\3\/LTDC_G4/SDMMC1_D0DIR/SDMMC2_D0DIR/USART6_CK E9 PF3/FMC_A3/I2C5_SDA/I2S3_WS/I2S4_SDI/LPTIM2_IN2/LTDC_G3/S\P\I\3\_\N\S\S\/SPI4_MISO B10 PF4/DCMIPP_D4/ETH2_RXD0/FMC_A4/L\T\D\C\_\B\6\/USART2_RX L2 PF5/DCMIPP_D11/DEBUG_TRACED12/DFSDM1_CKIN0/FMC_A5/I2C1_SMBA/LTDC_G0/LTDC_R5 B2 PF6/ETH2_TX_CTL/ETH2_TX_EN/LTDC_G4/LTDC_R7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX G2 PF7/ETH1_CLK125/ETH2_TXD0/FMC_A18/LTDC_G2/TIM17_CH1/UART4_CTS/UART7_TX M1 PF8/DCMIPP/LTDC/PWR/QUADSPI/SAI1/TIM13/TIM16/TIM4/TIM8/USART6 G5 PF9/DFSDM1/FMC/LTDC/QUADSPI/SAI1/TIM14/TIM17/TIM1/UART7/UART8 G1 PF10/DCMIPP/LTDC/QUADSPI/SAI1/SPI5/TAMP/TIM16/TIM8/UART7/USART6 G3 PF11/ADC1/ADC2/DFSDM1/ETH2/SAI1/USART2 T6 PF12/ADC1_INN2/ADC1_INP6/ETH1_CLK125/ETH1_TX_ER/I2S1_WS/SAI1_SD_A/S\P\I\1\_\N\S\S\/UART4_TX T4 PF13/ADC1/ADC2/DFSDM1/SAI1/TIM2/UART5/USART2 N6 PF14/DEBUG_JTCK-SWCLK P4 PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_JTMS-SWDIO R10 PF0/DEBUG_TRACED13/DFSDM1_CKOUT/FMC_A0/LTDC_G0/LTDC_R6/SDMMC2_D4/USART3_CK C13 PF1/DEBUG_TRACED7/FMC_A1/HDP_HDP7/I2C2_SDA/I2S3_SDO/L\T\D\C\_\B\7\/LTDC_G1/SPI3_MOSI B9 PF2/DEBUG_TRACED1/DFSDM1_CKIN1/FMC_A2/I2C2_SCL/L\T\D\C\_\B\3\/LTDC_G4/SDMMC1_D0DIR/SDMMC2_D0DIR/USART6_CK E9 PF3/FMC_A3/I2C5_SDA/I2S3_WS/I2S4_SDI/LPTIM2_IN2/LTDC_G3/S\P\I\3\_\N\S\S\/SPI4_MISO B10 PF4/DCMIPP_D4/ETH2_RXD0/FMC_A4/L\T\D\C\_\B\6\/USART2_RX L2 PF5/DCMIPP_D11/DEBUG_TRACED12/DFSDM1_CKIN0/FMC_A5/I2C1_SMBA/LTDC_G0/LTDC_R5 B2 PF6/ETH2_TX_CTL/ETH2_TX_EN/LTDC_G4/LTDC_R7/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\2\/S\P\I\5\_\N\S\S\/TIM16_CH1/UART7_RX G2 PF7/ETH1_CLK125/ETH2_TXD0/FMC_A18/LTDC_G2/TIM17_CH1/UART4_CTS/UART7_TX M1 PF8/DCMIPP/LTDC/PWR/QUADSPI/SAI1/TIM13/TIM16/TIM4/TIM8/USART6 G5 PF9/DFSDM1/FMC/LTDC/QUADSPI/SAI1/TIM14/TIM17/TIM1/UART7/UART8 G1 PF10/DCMIPP/LTDC/QUADSPI/SAI1/SPI5/TAMP/TIM16/TIM8/UART7/USART6 G3 PF11/ADC1/ADC2/DFSDM1/ETH2/SAI1/USART2 T6 PF12/ADC1_INN2/ADC1_INP6/ETH1_CLK125/ETH1_TX_ER/I2S1_WS/SAI1_SD_A/S\P\I\1\_\N\S\S\/UART4_TX T4 PF13/ADC1/ADC2/DFSDM1/SAI1/TIM2/UART5/USART2 N6 PF14/DEBUG_JTCK-SWCLK P4 PF15/ADC1_EXTI15/ADC2_EXTI15/DEBUG_JTMS-SWDIO R10
PG0/DCMIPP_PIXCLK/FDCAN2_TX/FMC_A10/LTDC_G5 D7 PG1/ETH2/FDCAN2/FMC/I2C2/I2S2/LPTIM1/LTDC/SAI2/SPI2/TIM4 N2 PG2/DCMIPP_D1/ETH1_MDC/RCC_MCO_2/S\A\I\2\_\M\C\L\K\_\B\/T\I\M\8\_\B\K\I\N\ R1 PG3/DCMIPP_D12/DCMIPP_D15/ETH1_MDIO/ETH2_GTX_CLK/FDCAN2_RX/FMC_A13/I2C2_SDA/S\A\I\2\_\S\D\_\B\/T\I\M\8\_\B\K\I\N\2\ L5 PG4/DCMIPP/DEBUG/DFSDM1/FMC/HDP/LTDC/SDMMC2/TIM1/USART3 A8 PG5/DCMIPP_D3/DCMIPP_VSYNC/ETH2_MDC/FMC_A15/LTDC_G4/TIM17_CH1 F2 PG6/DEBUG/HDP/LTDC/SAI2/SDMMC2/TIM17/TIM5/USART1 A14 PG7/DEBUG_TRACED8/I2S3_SDI/LTDC_R1/LTDC_R2/LTDC_R5/SDMMC2_CKIN/SPI3_MISO/TIM1_ETR/UART7_CTS C9 PG8/DCMIPP/ETH2/FMC/LTDC/QUADSPI/SAI1/SPDIFRX/SPI5/TAMP/TIM2/TIM8/USART3 F3 PG9/DCMIPP_VSYNC/DEBUG_DBTRGO/FDCAN1_RX/F\M\C\_\N\C\E\/F\M\C\_\N\E\2\/I2C2_SDA/SPDIFRX_IN3/USART6_RX E1 PG10/DCMIPP_D2/FDCAN1_TX/F\M\C\_\N\E\3\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/S\A\I\1\_\S\D\_\B\/SPI5_SCK/UART8_CTS F1 PG11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2S2/LTDC/SAI2/UART4/USART3 M3 PG12/ETH1/ETH2/LPTIM1/SAI2/USART3/USART6 T1 PG13/ADC2_INN2/ADC2_INP6/ETH1_TXD0/LPTIM1_OUT/USART6_CTS/U\S\A\R\T\6\_\N\S\S\ P8 PG14/ETH1_TXD1/LPTIM1_ETR/SAI2_D1/SAI2_SD_A/USART6_TX P9 PG15/ADC1/ADC2/DCMIPP/ETH2/LTDC/QUADSPI/UART7/USART6 G4 PG0/DCMIPP_PIXCLK/FDCAN2_TX/FMC_A10/LTDC_G5 D7 PG1/ETH2/FDCAN2/FMC/I2C2/I2S2/LPTIM1/LTDC/SAI2/SPI2/TIM4 N2 PG2/DCMIPP_D1/ETH1_MDC/RCC_MCO_2/S\A\I\2\_\M\C\L\K\_\B\/T\I\M\8\_\B\K\I\N\ R1 PG3/DCMIPP_D12/DCMIPP_D15/ETH1_MDIO/ETH2_GTX_CLK/FDCAN2_RX/FMC_A13/I2C2_SDA/S\A\I\2\_\S\D\_\B\/T\I\M\8\_\B\K\I\N\2\ L5 PG4/DCMIPP/DEBUG/DFSDM1/FMC/HDP/LTDC/SDMMC2/TIM1/USART3 A8 PG5/DCMIPP_D3/DCMIPP_VSYNC/ETH2_MDC/FMC_A15/LTDC_G4/TIM17_CH1 F2 PG6/DEBUG/HDP/LTDC/SAI2/SDMMC2/TIM17/TIM5/USART1 A14 PG7/DEBUG_TRACED8/I2S3_SDI/LTDC_R1/LTDC_R2/LTDC_R5/SDMMC2_CKIN/SPI3_MISO/TIM1_ETR/UART7_CTS C9 PG8/DCMIPP/ETH2/FMC/LTDC/QUADSPI/SAI1/SPDIFRX/SPI5/TAMP/TIM2/TIM8/USART3 F3 PG9/DCMIPP_VSYNC/DEBUG_DBTRGO/FDCAN1_RX/F\M\C\_\N\C\E\/F\M\C\_\N\E\2\/I2C2_SDA/SPDIFRX_IN3/USART6_RX E1 PG10/DCMIPP_D2/FDCAN1_TX/F\M\C\_\N\E\3\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/S\A\I\1\_\S\D\_\B\/SPI5_SCK/UART8_CTS F1 PG11/ADC1/ADC2/DCMIPP/ETH2/FMC/I2S2/LTDC/SAI2/UART4/USART3 M3 PG12/ETH1/ETH2/LPTIM1/SAI2/USART3/USART6 T1 PG13/ADC2_INN2/ADC2_INP6/ETH1_TXD0/LPTIM1_OUT/USART6_CTS/U\S\A\R\T\6\_\N\S\S\ P8 PG14/ETH1_TXD1/LPTIM1_ETR/SAI2_D1/SAI2_SD_A/USART6_TX P9 PG15/ADC1/ADC2/DCMIPP/ETH2/LTDC/QUADSPI/UART7/USART6 G4
PH0-OSC_IN/RCC_OSC_IN P1 PH1-OSC_OUT/RCC_OSC_OUT P2 PH2/DCMIPP/ETH1/ETH2/FMC/LPTIM1/LTDC/QUADSPI/UART7 F4 PH3/ETH1_COL/ETH2_COL/I2C3_SCL/L\T\D\C\_\B\4\/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/SPI5_MOSI R2 PH4/DEBUG_JTDI T15 PH5/DEBUG_JTDO-SWO R14 PH6/ETH1/ETH2/I2C5/I2S2/QUADSPI/SPI2/TIM12/USART2 L3 PH7/ETH1_TX_CLK/ETH2_TX_CLK/I2C3_SDA/L\T\D\C\_\B\2\/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/S\A\I\2\_\F\S\_\B\/SPI5_SCK H3 PH8/DCMIPP_HSYNC/DEBUG_TRACED9/FMC_A8/HDP_HDP2/I2C3_SDA/LTDC_R2/LTDC_R6/TIM5_ETR/USART2_RX F5 PH9/DCMIPP_D8/DCMIPP_D9/DCMIPP_D13/FMC_A20/I2S4_CK/L\T\D\C\_\B\5\/LTDC_DE/SPI4_SCK/TIM12_CH2/TIM1_CH4 A9 PH10/DEBUG/DFSDM1/HDP/I2S2/I2S3/LTDC/SAI2/SDMMC1/SPI2/TIM5/USART3 E11 PH11/ADC1/ADC2/ETH2/FMC/I2C4/I2S2/LTDC/QUADSPI/SAI2/SPI2/SPI5/TIM5/USART6 H1 PH12/DCMIPP/DFSDM1/ETH1/FMC/I2C3/QUADSPI/SAI1/SPI5/TIM5/USART2 C2 PH13/DEBUG_TRACED15/I2C5_SCL/I2S3_CK/LTDC_G2/LTDC_G3/SPI3_SCK/TIM8_CH1N/UART4_TX/USART2_CK A10 PH14/DCMIPP_D2/DCMIPP_D8/DCMIPP_PIXCLK/DFSDM1_DATIN2/I2C3_SDA/L\T\D\C\_\B\4\/UART4_RX B7 PI0/SPDIFRX_IN0/TAMP_IN8/TAMP_OUT1 L4 PI1/PWR_WKUP4/RTC_LSCO/RTC_LSCO_OUT2/RTC_OUT2/SPDIFRX_IN1/TAMP_IN2/TAMP_OUT3 K5 PI2/PWR_WKUP5/SPDIFRX_IN2/TAMP_IN3/TAMP_OUT4 J3 PI3/ETH1_RX_ER/PWR_WKUP2/SPDIFRX_IN3/TAMP_IN4/TAMP_OUT5 H2 PI4-BOOT0 U14 PI5-BOOT1 P12 PI6-BOOT2 R12 PI7/USB_OTG_HS_VBUS U16 PH0-OSC_IN/RCC_OSC_IN P1 PH1-OSC_OUT/RCC_OSC_OUT P2 PH2/DCMIPP/ETH1/ETH2/FMC/LPTIM1/LTDC/QUADSPI/UART7 F4 PH3/ETH1_COL/ETH2_COL/I2C3_SCL/L\T\D\C\_\B\4\/LTDC_R5/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\0\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\1\/SPI5_MOSI R2 PH4/DEBUG_JTDI T15 PH5/DEBUG_JTDO-SWO R14 PH6/ETH1/ETH2/I2C5/I2S2/QUADSPI/SPI2/TIM12/USART2 L3 PH7/ETH1_TX_CLK/ETH2_TX_CLK/I2C3_SDA/L\T\D\C\_\B\2\/Q\U\A\D\S\P\I\_\B\K\1\_\I\O\3\/Q\U\A\D\S\P\I\_\B\K\2\_\I\O\3\/S\A\I\2\_\F\S\_\B\/SPI5_SCK H3 PH8/DCMIPP_HSYNC/DEBUG_TRACED9/FMC_A8/HDP_HDP2/I2C3_SDA/LTDC_R2/LTDC_R6/TIM5_ETR/USART2_RX F5 PH9/DCMIPP_D8/DCMIPP_D9/DCMIPP_D13/FMC_A20/I2S4_CK/L\T\D\C\_\B\5\/LTDC_DE/SPI4_SCK/TIM12_CH2/TIM1_CH4 A9 PH10/DEBUG/DFSDM1/HDP/I2S2/I2S3/LTDC/SAI2/SDMMC1/SPI2/TIM5/USART3 E11 PH11/ADC1/ADC2/ETH2/FMC/I2C4/I2S2/LTDC/QUADSPI/SAI2/SPI2/SPI5/TIM5/USART6 H1 PH12/DCMIPP/DFSDM1/ETH1/FMC/I2C3/QUADSPI/SAI1/SPI5/TIM5/USART2 C2 PH13/DEBUG_TRACED15/I2C5_SCL/I2S3_CK/LTDC_G2/LTDC_G3/SPI3_SCK/TIM8_CH1N/UART4_TX/USART2_CK A10 PH14/DCMIPP_D2/DCMIPP_D8/DCMIPP_PIXCLK/DFSDM1_DATIN2/I2C3_SDA/L\T\D\C\_\B\4\/UART4_RX B7 PI0/SPDIFRX_IN0/TAMP_IN8/TAMP_OUT1 L4 PI1/PWR_WKUP4/RTC_LSCO/RTC_LSCO_OUT2/RTC_OUT2/SPDIFRX_IN1/TAMP_IN2/TAMP_OUT3 K5 PI2/PWR_WKUP5/SPDIFRX_IN2/TAMP_IN3/TAMP_OUT4 J3 PI3/ETH1_RX_ER/PWR_WKUP2/SPDIFRX_IN3/TAMP_IN4/TAMP_OUT5 H2 PI4-BOOT0 U14 PI5-BOOT1 P12 PI6-BOOT2 R12 PI7/USB_OTG_HS_VBUS U16
ST MICROELECTRONICS STM32MP135DAEX LFBGA289
Part ID
ST MICROELECTRONICS STM32MP135DAEX LFBGA289
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