mirror of
https://github.com/issus/altium-library.git
synced 2025-04-01 03:16:56 +00:00
Added Antenova SR42W001 3d model/footprint/symbol
This commit is contained in:
parent
004c337b85
commit
f39e9fe24f
@ -3,8 +3,6 @@ Version=1.0
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@ -33,6 +31,7 @@ FSMEncodingStyle=eFMSDropDownList_OneHot
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@ -89,7 +105,7 @@ DItemRevisionGUID=
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@ -106,7 +122,7 @@ DItemRevisionGUID=
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@ -123,7 +139,7 @@ DItemRevisionGUID=
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@ -157,7 +173,7 @@ DItemRevisionGUID=
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@ -174,7 +190,7 @@ DItemRevisionGUID=
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@ -191,7 +207,7 @@ DItemRevisionGUID=
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@ -208,7 +224,7 @@ DItemRevisionGUID=
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@ -225,7 +241,7 @@ DItemRevisionGUID=
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@ -242,7 +258,7 @@ DItemRevisionGUID=
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@ -259,7 +275,7 @@ DItemRevisionGUID=
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@ -276,7 +292,7 @@ DItemRevisionGUID=
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@ -293,7 +309,7 @@ DItemRevisionGUID=
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@ -310,7 +326,7 @@ DItemRevisionGUID=
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@ -327,7 +343,7 @@ DItemRevisionGUID=
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@ -344,7 +360,7 @@ DItemRevisionGUID=
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@ -361,7 +377,7 @@ DItemRevisionGUID=
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@ -378,7 +394,7 @@ DItemRevisionGUID=
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@ -395,7 +411,7 @@ DItemRevisionGUID=
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@ -412,7 +428,7 @@ DItemRevisionGUID=
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@ -429,7 +445,7 @@ DItemRevisionGUID=
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||||
DocumentPath=Footprints\LCD.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -973,7 +1006,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=
|
||||
|
||||
[Document56]
|
||||
[Document58]
|
||||
DocumentPath=Footprints\Leaded.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -990,7 +1023,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=QOSWIYRF
|
||||
|
||||
[Document57]
|
||||
[Document59]
|
||||
DocumentPath=Footprints\Leadless.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1007,7 +1040,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=YVUPUTLG
|
||||
|
||||
[Document58]
|
||||
[Document60]
|
||||
DocumentPath=Footprints\Mechanical.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1024,7 +1057,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=DAQVFDRN
|
||||
|
||||
[Document59]
|
||||
[Document61]
|
||||
DocumentPath=Footprints\Passives.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1041,7 +1074,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=JPLXECUF
|
||||
|
||||
[Document60]
|
||||
[Document62]
|
||||
DocumentPath=Footprints\Power Inductors.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1058,7 +1091,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=XWPUUYWV
|
||||
|
||||
[Document61]
|
||||
[Document63]
|
||||
DocumentPath=Footprints\Power Module.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1075,7 +1108,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=MGUEHMQD
|
||||
|
||||
[Document62]
|
||||
[Document64]
|
||||
DocumentPath=Footprints\QFN.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1092,7 +1125,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=AGEQQRLT
|
||||
|
||||
[Document63]
|
||||
[Document65]
|
||||
DocumentPath=Footprints\RF Connector.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1109,7 +1142,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=XWBILXQG
|
||||
|
||||
[Document64]
|
||||
[Document66]
|
||||
DocumentPath=Footprints\RF Filter.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1126,7 +1159,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=OXOQRWAV
|
||||
|
||||
[Document65]
|
||||
[Document67]
|
||||
DocumentPath=Footprints\RF Module.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1143,7 +1176,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=THNJVAWV
|
||||
|
||||
[Document66]
|
||||
[Document68]
|
||||
DocumentPath=Footprints\SpecialisedSensor.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1160,7 +1193,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=IKPWCXCL
|
||||
|
||||
[Document67]
|
||||
[Document69]
|
||||
DocumentPath=Footprints\Switch.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1177,7 +1210,7 @@ DItemRevisionGUID=
|
||||
GenerateClassCluster=0
|
||||
DocumentUniqueId=ETGVCBBD
|
||||
|
||||
[Document68]
|
||||
[Document70]
|
||||
DocumentPath=Footprints\Light Pipe.PcbLib
|
||||
AnnotationEnabled=1
|
||||
AnnotateStartValue=1
|
||||
@ -1204,36 +1237,106 @@ OutputName1=PCAD Netlist
|
||||
OutputDocumentPath1=
|
||||
OutputVariantName1=
|
||||
OutputDefault1=0
|
||||
OutputType2=SIMetrixNetlist
|
||||
OutputName2=SIMetrix
|
||||
OutputType2=XSpiceNetlist
|
||||
OutputName2=XSpice Netlist
|
||||
OutputDocumentPath2=
|
||||
OutputVariantName2=
|
||||
OutputDefault2=0
|
||||
OutputType3=SIMPLISNetlist
|
||||
OutputName3=SIMPLIS
|
||||
OutputType3=PADSNetlist
|
||||
OutputName3=PADS ASCII Netlist
|
||||
OutputDocumentPath3=
|
||||
OutputVariantName3=
|
||||
OutputDefault3=0
|
||||
OutputType4=Verilog
|
||||
OutputName4=Verilog File
|
||||
OutputType4=CadnetixNetlist
|
||||
OutputName4=Cadnetix Netlist
|
||||
OutputDocumentPath4=
|
||||
OutputVariantName4=
|
||||
OutputDefault4=0
|
||||
OutputType5=VHDL
|
||||
OutputName5=VHDL File
|
||||
OutputType5=CalayNetlist
|
||||
OutputName5=Calay Netlist
|
||||
OutputDocumentPath5=
|
||||
OutputVariantName5=
|
||||
OutputDefault5=0
|
||||
OutputType6=XSpiceNetlist
|
||||
OutputName6=XSpice Netlist
|
||||
OutputType6=EDIF
|
||||
OutputName6=EDIF for PCB
|
||||
OutputDocumentPath6=
|
||||
OutputVariantName6=
|
||||
OutputDefault6=0
|
||||
OutputType7=PADSNetlist
|
||||
OutputName7=PADS ASCII Netlist
|
||||
OutputType7=EESofNetlist
|
||||
OutputName7=EESof Netlist
|
||||
OutputDocumentPath7=
|
||||
OutputVariantName7=
|
||||
OutputDefault7=0
|
||||
OutputType8=IntergraphNetlist
|
||||
OutputName8=Intergraph Netlist
|
||||
OutputDocumentPath8=
|
||||
OutputVariantName8=
|
||||
OutputDefault8=0
|
||||
OutputType9=MentorBoardStationNetlist
|
||||
OutputName9=Mentor BoardStation Netlist
|
||||
OutputDocumentPath9=
|
||||
OutputVariantName9=
|
||||
OutputDefault9=0
|
||||
OutputType10=MultiWire
|
||||
OutputName10=MultiWire
|
||||
OutputDocumentPath10=
|
||||
OutputVariantName10=
|
||||
OutputDefault10=0
|
||||
OutputType11=OrCadPCB2Netlist
|
||||
OutputName11=Orcad/PCB2 Netlist
|
||||
OutputDocumentPath11=
|
||||
OutputVariantName11=
|
||||
OutputDefault11=0
|
||||
OutputType12=Pcad
|
||||
OutputName12=Pcad for PCB
|
||||
OutputDocumentPath12=
|
||||
OutputVariantName12=
|
||||
OutputDefault12=0
|
||||
OutputType13=PCADnltNetlist
|
||||
OutputName13=PCADnlt Netlist
|
||||
OutputDocumentPath13=
|
||||
OutputVariantName13=
|
||||
OutputDefault13=0
|
||||
OutputType14=Protel2Netlist
|
||||
OutputName14=Protel2 Netlist
|
||||
OutputDocumentPath14=
|
||||
OutputVariantName14=
|
||||
OutputDefault14=0
|
||||
OutputType15=ProtelNetlist
|
||||
OutputName15=Protel
|
||||
OutputDocumentPath15=
|
||||
OutputVariantName15=
|
||||
OutputDefault15=0
|
||||
OutputType16=RacalNetlist
|
||||
OutputName16=Racal Netlist
|
||||
OutputDocumentPath16=
|
||||
OutputVariantName16=
|
||||
OutputDefault16=0
|
||||
OutputType17=RINFNetlist
|
||||
OutputName17=RINF Netlist
|
||||
OutputDocumentPath17=
|
||||
OutputVariantName17=
|
||||
OutputDefault17=0
|
||||
OutputType18=SciCardsNetlist
|
||||
OutputName18=SciCards Netlist
|
||||
OutputDocumentPath18=
|
||||
OutputVariantName18=
|
||||
OutputDefault18=0
|
||||
OutputType19=TangoNetlist
|
||||
OutputName19=Tango Netlist
|
||||
OutputDocumentPath19=
|
||||
OutputVariantName19=
|
||||
OutputDefault19=0
|
||||
OutputType20=TelesisNetlist
|
||||
OutputName20=Telesis Netlist
|
||||
OutputDocumentPath20=
|
||||
OutputVariantName20=
|
||||
OutputDefault20=0
|
||||
OutputType21=WireListNetlist
|
||||
OutputName21=WireList Netlist
|
||||
OutputDocumentPath21=
|
||||
OutputVariantName21=
|
||||
OutputDefault21=0
|
||||
|
||||
[OutputGroup2]
|
||||
Name=Simulator Outputs
|
||||
@ -1245,148 +1348,96 @@ OutputName1=Mixed Sim
|
||||
OutputDocumentPath1=
|
||||
OutputVariantName1=
|
||||
OutputDefault1=0
|
||||
OutputType2=SIMetrixSimulation
|
||||
OutputName2=SIMetrix
|
||||
OutputDocumentPath2=
|
||||
OutputVariantName2=
|
||||
OutputDefault2=0
|
||||
OutputType3=SIMPLISSimulation
|
||||
OutputName3=SIMPLIS
|
||||
OutputDocumentPath3=
|
||||
OutputVariantName3=
|
||||
OutputDefault3=0
|
||||
|
||||
[OutputGroup3]
|
||||
Name=Documentation Outputs
|
||||
Description=
|
||||
TargetPrinter=Virtual Printer
|
||||
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
|
||||
OutputType1=Assembler Source Print
|
||||
OutputName1=Assembler Source Prints
|
||||
OutputType1=Composite
|
||||
OutputName1=Composite Drawing
|
||||
OutputDocumentPath1=
|
||||
OutputVariantName1=
|
||||
OutputDefault1=0
|
||||
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType2=C Source Print
|
||||
OutputName2=C Source Prints
|
||||
OutputType2=PCB 3D Print
|
||||
OutputName2=PCB 3D Print
|
||||
OutputDocumentPath2=
|
||||
OutputVariantName2=
|
||||
OutputVariantName2=[No Variations]
|
||||
OutputDefault2=0
|
||||
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType3=C/C++ Header Print
|
||||
OutputName3=C/C++ Header Prints
|
||||
OutputType3=PCB 3D Video
|
||||
OutputName3=PCB 3D Video
|
||||
OutputDocumentPath3=
|
||||
OutputVariantName3=
|
||||
OutputVariantName3=[No Variations]
|
||||
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||||
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType4=C++ Source Print
|
||||
OutputName4=C++ Source Prints
|
||||
OutputType4=PCB Print
|
||||
OutputName4=PCB Prints
|
||||
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|
||||
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|
||||
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|
||||
PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType5=Composite
|
||||
OutputName5=Composite Drawing
|
||||
OutputDocumentPath5=
|
||||
OutputType5=PCBLIB Print
|
||||
OutputName5=PCBLIB Prints
|
||||
OutputDocumentPath5=D:\altium-library\Footprints\Leaded.PcbLib
|
||||
OutputVariantName5=
|
||||
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||||
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|
||||
OutputType6=FSM Print
|
||||
OutputName6=FSM Prints
|
||||
Configuration5_Name1=OutputConfigurationParameter1
|
||||
Configuration5_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView
|
||||
Configuration5_Name2=OutputConfigurationParameter2
|
||||
Configuration5_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False
|
||||
Configuration5_Name3=OutputConfigurationParameter3
|
||||
Configuration5_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
|
||||
Configuration5_Name4=OutputConfigurationParameter4
|
||||
Configuration5_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
|
||||
Configuration5_Name5=OutputConfigurationParameter5
|
||||
Configuration5_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
|
||||
Configuration5_Name6=OutputConfigurationParameter6
|
||||
Configuration5_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
|
||||
OutputType6=Report Print
|
||||
OutputName6=Report Prints
|
||||
OutputDocumentPath6=
|
||||
OutputVariantName6=
|
||||
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|
||||
PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType7=OpenBus Print
|
||||
OutputName7=OpenBus Prints
|
||||
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|
||||
OutputName7=Schematic Prints
|
||||
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|
||||
OutputVariantName7=
|
||||
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|
||||
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|
||||
OutputType8=PCB 3D Print
|
||||
OutputName8=PCB 3D Print
|
||||
OutputType8=SimView Print
|
||||
OutputName8=SimView Prints
|
||||
OutputDocumentPath8=
|
||||
OutputVariantName8=[No Variations]
|
||||
OutputVariantName8=
|
||||
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|
||||
PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType9=PCB 3D Video
|
||||
OutputName9=PCB 3D Video
|
||||
OutputType9=Wave Print
|
||||
OutputName9=Wave Prints
|
||||
OutputDocumentPath9=
|
||||
OutputVariantName9=[No Variations]
|
||||
OutputVariantName9=
|
||||
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|
||||
PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType10=PCB Print
|
||||
OutputName10=PCB Prints
|
||||
OutputType10=WaveSim Print
|
||||
OutputName10=WaveSim Prints
|
||||
OutputDocumentPath10=
|
||||
OutputVariantName10=
|
||||
OutputDefault10=0
|
||||
PageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
OutputType11=PCBLIB Print
|
||||
OutputName11=PCBLIB Prints
|
||||
OutputDocumentPath11=D:\altium-library\Footprints\Leaded.PcbLib
|
||||
OutputType11=PCBDrawing
|
||||
OutputName11=Draftsman
|
||||
OutputDocumentPath11=
|
||||
OutputVariantName11=
|
||||
OutputDefault11=0
|
||||
PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
|
||||
Configuration11_Name1=OutputConfigurationParameter1
|
||||
Configuration11_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView
|
||||
Configuration11_Name2=OutputConfigurationParameter2
|
||||
Configuration11_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False
|
||||
Configuration11_Name3=OutputConfigurationParameter3
|
||||
Configuration11_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer
|
||||
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@ -1763,6 +1814,42 @@ OutputName4=Export STEP
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[Modification Levels]
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@ -1845,6 +1932,16 @@ Type77=1
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[Difference Levels]
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@ -1892,6 +1989,10 @@ Type42=1
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[Electrical Rules Check]
|
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Type1=1
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@ -2005,6 +2106,8 @@ Type108=2
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[ERC Connection Matrix]
|
||||
L1=NNNNNNNNNNNWNNNWW
|
||||
|
Footprints/Antenna.PcbLib
Normal file
LOADING design file
689
STEP/Antenna/Antenova SR42W001_Mutica.STEP
Normal file
689
STEP/Antenna/Antenova SR42W001_Mutica.STEP
Normal file
@ -0,0 +1,689 @@
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ISO-10303-21;
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HEADER;
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||||
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||||
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|
||||
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END-ISO-10303-21;
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Symbols/Antenna.SchLib
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Reference in New Issue
Block a user