Merge branch 'main' of git.beagleboard.org:lorforlinux/beaglev-fire; branch 'main' of https://git.beagleboard.org/beaglev-fire/beaglev-fire

default-load/polarbone/polarbone.prjx

@@ -1,184 +0,0 @@
-KEY LIBERO "2021.1"
-KEY CAPTURE "2021.1.0.17"
-KEY DEFAULT_IMPORT_LOC ""
-KEY ProjectID "0"
-KEY HDLTechnology "VERILOG"
-KEY VERILOGMODE "SYSTEMVERILOG"
-KEY VHDLMODE "VHDL2008"
-KEY SYSTEMVERILOGMFCU "FALSE"
-KEY UseConstraintFlowTechnology "TRUE"
-KEY VendorTechnology_Family "PolarFireSoC"
-KEY VendorTechnology_Die "PA5SOC250T"
-KEY VendorTechnology_Package "fcvg484"
-KEY VendorTechnology_Speed "STD"
-KEY VendorTechnology_DieVoltage "1.05"
-KEY VendorTechnology_PART_RANGE "EXT"
-KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE ""
-KEY VendorTechnology_IO_DEFT_STD "LVCMOS33"
-KEY VendorTechnology_OPCONR ""
-KEY VendorTechnology_PLL_SUPPLY ""
-KEY VendorTechnology_RAD_EXPOSURE ""
-KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
-KEY VendorTechnology_RESTRICTPROBEPINS "1"
-KEY VendorTechnology_RESTRICTSPIPINS "0"
-KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
-KEY VendorTechnology_TARGETDEVICESFORMIGRATION "PA5SOC250T"
-KEY VendorTechnology_TEMPR "EXT"
-KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
-KEY VendorTechnology_VCCI_1.2_VOLTR "EXT"
-KEY VendorTechnology_VCCI_1.5_VOLTR "EXT"
-KEY VendorTechnology_VCCI_1.8_VOLTR "EXT"
-KEY VendorTechnology_VCCI_2.5_VOLTR "EXT"
-KEY VendorTechnology_VCCI_3.3_VOLTR "EXT"
-KEY VendorTechnology_VOLTR "EXT"
-KEY ProjectLocation "/home/jkridner/polarbone/default-load/polarbone"
-KEY ProjectDescription ""
-KEY UseRootLocationForLinkedFiles "FALSE"
-KEY RootLocationENVForLinkedFiles ""
-KEY RootLocationForLinkedFiles ""
-KEY GlobalIncludePaths ""
-KEY Pa4PeripheralNewSeq "GOOD"
-KEY SimulationType "VERILOG"
-KEY Vendor "Actel"
-LIST REVISIONS
-VALUE="Impl1",NUM=1
-CURREV=1
-ENDLIST
-LIST GlobalIncludeFileList
-ENDLIST
-LIST FileManager
-ENDLIST
-LIST UsedFile
-ENDLIST
-LIST NewModulesInfo
-ENDLIST
-LIST AssociatedStimulus
-ENDLIST
-LIST Other_Association
-ENDLIST
-LIST SimulationOptions
-UseAutomaticDoFile=true
-IncludeWaveDo=false
-Type=max
-RunTime=1000ns
-Resolution=1ps
-VsimOpt=
-EntityName=testbench
-TopInstanceName=<top>_0
-DoFileName=
-DoFileName2=wave.do
-DoFileParams=
-DisplayDUTWave=false
-LogAllSignals=false
-DisablePulseFiltering=false
-DumpVCD=false
-VCDFileName=power.vcd
-VHDL2008=false
-Verilog2001=false
-SystemVerilog=false
-TimeUnit=1
-TimeUnitBase=ns
-Precision=100
-PrecisionBase=ps
-SdfCorner=slow_lv_ht
-PliPath=/opt/microsemi/Libero_SoC_v2021.1/Libero/lib/modelsimpro/pli/pf_crypto_lin_me_pli.so
-UseCustomPliPath=false
-ENDLIST
-LIST ModelSimLibPath
-UseCustomPath=FALSE
-LibraryPath=
-ENDLIST
-LIST GlobalFlowOptions
-GenerateHDLAfterSynthesis=FALSE
-GenerateHDLAfterPhySynthesis=FALSE
-RunDRCAfterSynthesis=FALSE
-AutoCheckConstraints=TRUE
-UpdateModelSimIni=TRUE
-NoIOMode=FALSE
-PeriInitStandalone=FALSE
-OnDemandBuildDH=TRUE
-EnableViewDraw=FALSE
-UpdateViewDrawIni=TRUE
-GenerateHDLFromSchematic=TRUE
-VmNetlistFlowOn=TRUE
-EnableDesignSeparationOn=FALSE
-EnableSETMitigationOn=FALSE
-DisplayFanoutLimit=10
-AbortFlowOnPDCErrorsOn=TRUE
-AbortFlowOnSDCErrorsOn=TRUE
-AbortFlowOn3.3V_IO_ON=FALSE
-InstantiateInSmartDesign=TRUE
-FlashProInputFile=pdb
-SmartGenCompileReport=T
-ENDLIST
-LIST PhySynthesisOptions
-ENDLIST
-LIST Profiles
-NAME="SoftConsole"
-FUNCTION="SoftwareIDE"
-TOOL="SoftConsole"
-LOCATION="eclipse.exe"
-PARAM=""
-BATCH=0
-LICENSE=""
-IS32BIT="1"
-EndProfile
-NAME="Synplify Pro ME"
-FUNCTION="Synthesis"
-TOOL="Synplify Pro ME"
-LOCATION="/opt/microsemi/Libero_SoC_v2021.1/SynplifyPro/bin/synplify_pro"
-PARAM=""
-BATCH=0
-LICENSE=""
-IS32BIT="1"
-EndProfile
-NAME="ModelSim ME Pro"
-FUNCTION="Simulation"
-TOOL="ModelSim Pro Edition"
-LOCATION="/opt/microsemi/Libero_SoC_v2021.1/ModelSimPro/modeltech/linuxacoem/vsim"
-PARAM=""
-BATCH=0
-LICENSE=""
-IS32BIT="1"
-EndProfile
-NAME="Identify Debugger"
-FUNCTION="IdentifyDebugger"
-TOOL="Identify Debugger"
-LOCATION="/opt/microsemi/Libero_SoC_v2021.1/Identify/bin/identify_debugger"
-PARAM=""
-BATCH=0
-LICENSE=""
-IS32BIT="1"
-EndProfile
-ENDLIST
-LIST ProjectState5.1
-ENDLIST
-LIST ExcludePackageForSimulation
-ENDLIST
-LIST ExcludePackageForSynthesis
-ENDLIST
-LIST IncludeModuleForSimulation
-ENDLIST
-LIST CDBOrder
-ENDLIST
-LIST UserCustomizedFileList
-ENDLIST
-LIST OpenedFileList
-ORIENTATION;HORIZONTAL
-Reports;Reports;0
-ReportsCurrentItem;Project Summary:polarbone.log
-StartPage;StartPage;0
-ACTIVEVIEW;Reports
-ENDLIST
-LIST ModuleSubBlockList
-ENDLIST
-LIST ActiveTestBenchList
-ENDLIST
-LIST IOTabList
-ENDLIST
-LIST FPTabList
-ENDLIST
-LIST TimingTabList
-ENDLIST
-LIST FDCTabList
-ENDLIST

default-load/polarbone/simulation/modelsim.ini

@@ -1,10 +0,0 @@
-[Library]
-others = $MODEL_TECH/../modelsim.ini
-polarfire = /opt/microsemi/Libero_SoC_v2021.1/Libero/lib/modelsimpro/precompiled/vlog/polarfire
-syncad_vhdl_lib = /opt/microsemi/Libero_SoC_v2021.1/Libero/lib/actel/syncad_vhdl_lib
-
-[vcom]
-VHDL93 = 1
-
-[vsim]
-IterationLimit = 5000

default-load/polarbone/smartgen/smartgen.aws

@@ -1 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="F"/></reports><subproject libero="T"/><hdltype>Verilog</hdltype><componentInstances/><device die="PA5SOC250T" family="PolarFireSoC" package="fcvg484"/><SmartGen version="8.0"/></workspace>

default-load/polarbone/tooldata/libero.1809407

@@ -1,3 +0,0 @@
-libero
-1
-libero,1809407:40989:0

default-load/polarbone/tooldata/polarbone.log

@@ -1,16 +0,0 @@
-Project Name: polarbone
-Location: /home/jkridner/polarbone/default-load/polarbone
-Description: 
-Preferred HDL Type: Verilog
-
-#-----------------------------------------------------
-                  Device Details
-#-----------------------------------------------------
-
-Part Number    : MPFS250T-FCVG484E
-Family         : PolarFireSoC
-Die            : MPFS250T
-Package        : FCVG484
-Speed          : STD
-Core Voltage   : 1.05
-Range          : EXT

default-load/polarbone/viewdraw/vf/project.lst

@@ -1,2 +0,0 @@
-0
-/home/jkridner/polarbone/default-load/polarbone/viewdraw/ viewdraw

default-load/polarbone/viewdraw/viewdraw.ini

@@ -1,63 +0,0 @@
-NET               12      1       0
-COMPONENT         15      0       0
-ATTRIBUTE         14      0       0
-LABEL             15      0       0
-PIN                3      0       0
-BOX                2      0       0
-LINE               2      0       0
-CIRCLE             2      0       0
-ARC                2      0       0
-TEXT              10      0       0
-SELECTION_LAYER   15      0       0
-BORDER_LAYER      15      0       0
-VALUE_LAYER        7      0       0
-ANNO_LAYER         7      0       0
-GRID            10 
-DOTSIZE          5
-BUS_DOTSIZE     12
-BOXSIZE          5
-TEXTSIZE        10
-TEXTORIGIN       3
-BUSWIDTH         4
-BUBBLESIZE       5
-AUTOLOG         10
-SDISTANCE       10
-ADISTANCE       20
-SHEETSIZE        1
-ROUTE            2
-SCOPE            0
-TEXT_THRESHOLD   3
-NEW_ATTR_VIS     1
-BLOCKTYPE        0
-UNDO             16
-GRIDON           1 
-BORDERON         1 
-HEADERON         1 
-COMPTEXTON       1 
-TEXTON           1 
-ATTRON           1 
-LABELON          1 
-DETAIL           1 
-SNAPTOPIN        1 
-UNIQUE_LABEL     0 
-VALUESON         1 
-CONTEXT_WINDOW   0 
-NAMESON          0 
-SORTON           1 
-PNUMSON          1 
-RNUMSON          1 
-DEFSHEET         0 
-XTRAERRS         1 
-DBOXON           0 
-PRESERVE_CASE    0 
-ALLOW_VALUE_MIXED VERILOG
-NETNAME VDD        
-NETNAME GND        
-ATTR_RESET SS#1
-ATTR_RESET SS#2
-ATTR_RESET ALL_ID 
-ATTR_RESET GEN_ID 
-ATTR_RESET REFDES SYMBOL_VALUE
-DIR [pw] /home/jkridner/polarbone/default-load/polarbone/viewdraw
-DIR [rm] /opt/microsemi/Libero_SoC_v2021.1/Libero/lib/libvd/PolarFireSoC/cells (actelcells)
-DIR [rm] /opt/microsemi/Libero_SoC_v2021.1/Libero/lib/libvd/asicbin (builtin)