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https://gitlab.com/zephray/glider.git
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130 lines
4.7 KiB
C
130 lines
4.7 KiB
C
//
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// Grimoire
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// Copyright 2025 Wenting Zhang
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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#include "platform.h"
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#include "board.h"
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#include "app.h"
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static size_t last_update;
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static size_t last_update_duration;
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static uint8_t waveform_frames;
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static uint8_t get_update_frames(void) {
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// Should be worst case time to clear/ update a frame
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//uint8_t min_time = 10; // Minimum time for non-LUT modes
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// actually, just always return 0.5s
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return 16;
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}
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static void wait(void) {
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// Reading is not implemented in the simulator
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}
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void caster_init(void) {
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waveform_frames = 38; // Need to sync with the RTL code
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fpga_write_reg8(CSR_CFG_V_FP, config.tcon_vfp);
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fpga_write_reg8(CSR_CFG_V_SYNC, config.tcon_vsync);
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fpga_write_reg8(CSR_CFG_V_BP, config.tcon_vbp);
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fpga_write_reg16(CSR_CFG_V_ACT, config.tcon_vact);
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fpga_write_reg8(CSR_CFG_H_FP, config.tcon_hfp);
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fpga_write_reg8(CSR_CFG_H_SYNC, config.tcon_hsync);
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fpga_write_reg8(CSR_CFG_H_BP, config.tcon_hbp);
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fpga_write_reg16(CSR_CFG_H_ACT, config.tcon_hact);
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uint32_t frame_bytes = config.tcon_hact * 4 * config.tcon_vact * 2;
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fpga_write_reg8(CSR_CFG_FBYTES_B0, frame_bytes & 0xff);
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fpga_write_reg8(CSR_CFG_FBYTES_B1, (frame_bytes >> 8) & 0xff);
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fpga_write_reg8(CSR_CFG_FBYTES_B2, (frame_bytes >> 16) & 0xff);
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fpga_write_reg8(CSR_CFG_MINDRV, 2);
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fpga_write_reg8(CSR_LUT_FRAME, 38);
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fpga_write_reg16(CSR_OSD_LEFT, 0);
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fpga_write_reg16(CSR_OSD_RIGHT, 256/4);
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fpga_write_reg16(CSR_OSD_TOP, 0);
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fpga_write_reg16(CSR_OSD_BOTTOM, 128);
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fpga_write_reg8(CSR_OSD_EN, 0);
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fpga_write_reg8(CSR_CFG_MIRROR, config.mirror);
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fpga_write_reg8(CSR_ENABLE, 1); // Enable refresh
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}
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static uint8_t is_busy() {
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uint8_t status = fpga_write_reg8(CSR_STATUS, 0x00);
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return !!(status & STATUS_OP_QUEUE);
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}
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uint8_t caster_load_waveform(uint8_t *waveform, uint8_t frames) {
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fpga_write_reg8(CSR_LUT_FRAME, 0); // Reset value before loading
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fpga_write_reg16(CSR_LUT_ADDR, 0);
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fpga_write_bulk(CSR_LUT_WR, waveform, WAVEFORM_SIZE);
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waveform_frames = frames;
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return 0;
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}
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uint8_t caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
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//if (is_busy()) return 1;
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fpga_write_reg16(CSR_OP_LEFT, x0);
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fpga_write_reg16(CSR_OP_TOP, y0);
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fpga_write_reg16(CSR_OP_RIGHT, x1);
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fpga_write_reg16(CSR_OP_BOTTOM, y1);
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fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
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fpga_write_reg8(CSR_OP_CMD, OP_EXT_REDRAW);
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return 0;
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}
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uint8_t caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
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update_mode_t mode) {
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//if (is_busy()) return 1;
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fpga_write_reg16(CSR_OP_LEFT, x0);
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fpga_write_reg16(CSR_OP_TOP, y0);
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fpga_write_reg16(CSR_OP_RIGHT, x1);
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fpga_write_reg16(CSR_OP_BOTTOM, y1);
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fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
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fpga_write_reg8(CSR_OP_PARAM, (uint8_t)mode);
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fpga_write_reg8(CSR_OP_CMD, OP_EXT_SETMODE);
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return 0;
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}
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uint8_t caster_setinput(uint8_t input_src) {
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// if (is_busy()) return 1;
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// fpga_write_reg8(CSR_CFG_IN_SRC, input_src);
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return 0;
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}
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void caster_redraw_blank(void) {
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fpga_write_reg16(CSR_OP_LEFT, 0);
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fpga_write_reg16(CSR_OP_TOP, 0);
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fpga_write_reg16(CSR_OP_RIGHT, config.hact);
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fpga_write_reg16(CSR_OP_BOTTOM, config.vact);
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fpga_write_reg8(CSR_OP_LENGTH, get_update_frames());
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fpga_write_reg8(CSR_ENABLE, 0x3); // Enable blanking
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fpga_write_reg8(CSR_OP_CMD, OP_EXT_REDRAW);
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}
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uint8_t caster_osd_send_buf(uint8_t *buf) {
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fpga_write_reg16(CSR_OSD_ADDR, 0);
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fpga_write_bulk(CSR_OSD_WR, buf, 4096);
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return 0;
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}
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uint8_t caster_osd_set_enable(bool en) {
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fpga_write_reg8(CSR_OSD_EN, en);
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return 0;
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}
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