96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
//
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// Caster simulator
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// Copyright 2023 Wenting Zhang
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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#pragma once
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// Register map
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#define CSR_LUT_FRAME 0
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#define CSR_LUT_ADDR_HI 1
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#define CSR_LUT_ADDR_LO 2
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#define CSR_LUT_WR 3
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#define CSR_OP_LEFT_HI 4
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#define CSR_OP_LEFT_LO 5
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#define CSR_OP_RIGHT_HI 6
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#define CSR_OP_RIGHT_LO 7
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#define CSR_OP_TOP_HI 8
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#define CSR_OP_TOP_LO 9
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#define CSR_OP_BOTTOM_HI 10
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#define CSR_OP_BOTTOM_LO 11
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#define CSR_OP_PARAM 12
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#define CSR_OP_LENGTH 13
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#define CSR_OP_CMD 14
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#define CSR_CONTROL 15
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#define CSR_CFG_V_FP 16
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#define CSR_CFG_V_SYNC 17
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#define CSR_CFG_V_BP 18
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#define CSR_CFG_V_ACT_HI 19
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#define CSR_CFG_V_ACT_LO 20
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#define CSR_CFG_H_FP 21
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#define CSR_CFG_H_SYNC 22
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#define CSR_CFG_H_BP 23
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#define CSR_CFG_H_ACT_HI 24
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#define CSR_CFG_H_ACT_LO 25
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#define CSR_CFG_FBYTES_B2 27
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#define CSR_CFG_FBYTES_B1 28
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#define CSR_CFG_FBYTES_B0 29
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// Alias for 16bit registers
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#define CSR_LUT_ADDR CSR_LUT_ADDR_HI
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#define CSR_OP_LEFT CSR_OP_LEFT_HI
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#define CSR_OP_RIGHT CSR_OP_RIGHT_HI
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#define CSR_OP_TOP CSR_OP_TOP_HI
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#define CSR_OP_BOTTOM CSR_OP_BOTTOM_HI
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#define CSR_CFG_V_ACT CSR_CFG_V_ACT_HI
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#define CSR_CFG_H_ACT CSR_CFG_H_ACT_HI
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// Commands
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#define OP_EXT_REDRAW 0
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#define OP_EXT_SETMODE 1
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// Status bits
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#define STATUS_MIG_ERROR 7
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#define STATUS_MIF_ERROR 6
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#define STATUS_SYS_READY 5
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#define STATUS_OP_BUSY 4
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#define STATUS_OP_QUEUE 3
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#define CTRL_ENABLE 0
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#define WAVEFORM_SIZE (4*1024)
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#define FRAME_RATE_HZ (60)
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typedef enum {
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UM_MANUAL_LUT_NO_DITHER = 0,
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UM_MANUAL_LUT_ERROR_DIFFUSION = 1,
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UM_FAST_MONO_NO_DITHER = 2,
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UM_FAST_MONO_BAYER = 3,
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UM_FAST_MONO_BLUE_NOISE = 4,
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UM_FAST_GREY = 5,
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UM_AUTO_LUT_NO_DITHER = 6,
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UM_AUTO_LUT_ERROR_DIFFUSION = 7
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} UPDATE_MODE;
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void caster_init(void);
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void caster_load_waveform(uint8_t *waveform, uint8_t frames);
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void caster_redraw(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);
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void caster_setmode(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1,
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UPDATE_MODE mode);
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