mirror of
https://github.com/gusmanb/logicanalyzer.git
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206 lines
7.0 KiB
Plaintext
206 lines
7.0 KiB
Plaintext
; Generated by JITX 3.16.0
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#use-added-syntax(jitx)
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defpackage main :
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import core
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import jitx
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import jitx/commands
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import ocdb/utils/generic-components
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import helpers
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; Define the shape/size of the board
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val board-shape = RoundedRectangle(55.5, 65.0, 0.25)
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pcb-routing-structure data-line :
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name = "Capture data line"
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layer-constraints(Top) :
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trace-width = 0.13 ; mm
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clearance = 0.1 ; mm
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velocity = 0.19e12 ; mm/s
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insertion-loss = 0.008 ; db/mm @ 1GHz
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layer-constraints(Bottom) :
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trace-width = 0.13 ; mm
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clearance = 0.1 ; mm
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velocity = 0.19e12 ; mm/s
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insertion-loss = 0.008 ; db/mm @ 1GHz
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; Module to run as a design
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pcb-module logic-analyzer :
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node gnd:pin
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; Level shifters
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var shifters = Array<?>(6)
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var shifterInputPins = Array<?>(24)
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var shifterOutputPins = Array<?>(24)
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var shifterRefAPins = Array<?>(6)
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var shifterRefBPins = Array<?>(6)
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for i in 0 to 6 :
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println("Instantiating shifter %_" % [i])
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inst shifter : database-part(["mpn" => "TXU0104PWR", "manufacturer" => "Texas Instruments"])
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net (shifter.GND, gnd)
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shifters[i] = shifter
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val offset = i * 4
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shifterInputPins[offset] = shifter.A1
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shifterInputPins[offset + 1] = shifter.A2
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shifterInputPins[offset + 2] = shifter.A3
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shifterInputPins[offset + 3] = shifter.A4
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shifterOutputPins[offset] = shifter.B1Y
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shifterOutputPins[offset + 1] = shifter.B2Y
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shifterOutputPins[offset + 2] = shifter.B3Y
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shifterOutputPins[offset + 3] = shifter.B4Y
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shifterRefAPins[i] = shifter.VCCA
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shifterRefBPins[i] = shifter.VCCB
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;Pico module
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inst U7 : database-part(["mpn" => "PICO", "manufacturer" => "Raspberry Pi"])
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;Pin headers
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inst J1 : database-part(["mpn" => "SK13D07VG5", "manufacturer" => "SHOU HAN"]);database-part(["mpn" => "SK-13D01-G030", "manufacturer" => "G-Switch"])
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inst J2 : database-part(["mpn" => "C97095", "manufacturer" => "BOOMELE"]);database-part(["mpn" => "S108500004", "manufacturer" => "Ckmtw(Shenzhen Cankemeng)"])
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inst J3 : database-part(["mpn" => "PM254-1-03-W-8.5", "manufacturer" => "HCTL"])
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inst J4 : database-part(["mpn" => "DZ254W-11-03-65", "manufacturer" => "DEALON"])
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;Diodes
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inst D1 : database-part(["mpn" => "LL4148", "manufacturer" => "MDD（Microdiode Electronics）"])
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;Resistors
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inst r1 : chip-resistor(8.2e3)
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inst r2 : chip-resistor(100.0e3)
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;VREF nets
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net VREF (shifters[0].VCCA, shifters[1].VCCA, shifters[2].VCCA, shifters[3].VCCA, shifters[4].VCCA, shifters[5].VCCA, J1.p[2])
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net EXT_VREF (J1.p[1], J2.p[3])
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property(VREF.voltage) = tol%(5.0, 5.0)
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property(EXT_VREF.voltage) = tol%(5.0, 5.0)
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;Power nets
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net POWER_3v3 (shifters[0].OE, shifters[1].OE, shifters[2].OE, shifters[3].OE, shifters[4].OE, shifters[5].OE, shifters[0].VCCB, shifters[1].VCCB , shifters[2].VCCB , shifters[3].VCCB , shifters[4].VCCB , shifters[5].VCCB , J1.p[3] , J2.p[7] , J2.p[8] , U7.P_3V3_OUT) ; 3v3
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net POWER_5v (J1.p[4] , U7.VBUS , J2.p[5] , J2.p[6]) ; 5v
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net GND (U7.GND0 , U7.GND1 , U7.GND2 , U7.GND3 , U7.GND4 , U7.GND6 , U7.GND6 , U7.GND7 , J2.p[1] , J2.p[2] , J3.p[3] , J4.p[3] , r1.p[2] , r2.p[2] , gnd) ; gnd
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property(POWER_3v3.voltage) = tol%(3.3, 5.0)
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property(POWER_5v.voltage) = tol%(5.0, 5.0)
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property(GND.voltage) = typ(0.0)
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;Trigger nets
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net EXT_CHAIN (D1.A, U7.GP0, U7.GP1, J3.p[1], J4.p[1], r1.p[1])
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net EXT_TRIG (D1.C, J2.p[4], r2.p[1])
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property(EXT_CHAIN.voltage) = tol%(3.3, 5.0)
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property(EXT_TRIG.voltage) = tol%(3.3, 5.0)
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; Decoupling caps
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for i in 0 to 6 :
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println("Creating decoupling caps for shifter %_" % [i])
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bypass-cap-strap(shifters[i].VCCA, gnd, 100.0e-9)
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bypass-cap-strap(shifters[i].VCCB, gnd, 100.0e-9)
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val signal-skew = TimingDifferenceConstraint(0.0 +/- 50.0e-12) ;50 picosec
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;Shifter input nets
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for i in 0 to 24 :
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var pinNum
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var netName
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if i < 12 :
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pinNum = 31 - (i * 2)
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netName = to-symbol("DIN%_" % [i + 1])
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else :
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pinNum = 32 - ((i - 12) * 2)
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netName = to-symbol("DIN%_" % [24 - (i - 12)])
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println("Mapping shifter input pin %_ to connector pin %_" % [i, pinNum])
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;val netName = to-symbol("DIN%_" % [i + 1])
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make-net(netName, [shifterInputPins[i], J2.p[pinNum]])
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println("Creating topology from shifterInputPins[%_] to J2.p[%_]" % [i, pinNum])
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topology-segment(shifterInputPins[i], J2.p[pinNum])
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structure(shifterInputPins[i] => J2.p[pinNum]) = data-line
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if i < 23 :
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println("Creating timming constraing for shifterInputPins[%_] => J2.p[%_], shifterInputPins[23] => J2.p[10]" % [ i, pinNum ])
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timing-difference(
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shifterInputPins[i] => J2.p[pinNum],
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shifterInputPins[23] => J2.p[10],
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) = signal-skew
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var gpNum
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var o
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if i < 21 :
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gpNum = i + 2
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else :
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gpNum = i + 5
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if i < 12 :
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o = i
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else :
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o = 11 + (24 - i)
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println("Mapping shifter output pin %_ to gpio %_" % [o, gpNum])
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val outNetName = to-symbol("DOUT%_" % [i + 1])
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make-net(outNetName, [shifterOutputPins[o], U7.(to-symbol("GP%_" % [gpNum]))])
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println("Creating topology from shifterOutputPins[%_] to U7.GP%_" % [o, gpNum])
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topology-segment(shifterOutputPins[o], U7.(to-symbol("GP%_" % [gpNum])))
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structure(shifterOutputPins[o] => U7.(to-symbol("GP%_" % [gpNum]))) = data-line
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if o < 23 :
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println("Creating timming constraing for shifterOutputPins[%_] => U7.GP%_, shifterOutputPins[23] => U7.GP14" % [ i, gpNum ])
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timing-difference(
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shifterOutputPins[o] => U7.(to-symbol("GP%_" % [gpNum])),
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shifterOutputPins[23] => U7.GP14,
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) = signal-skew
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geom(GND) :
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copper-pour(LayerIndex(0), isolate = 0.1) = RoundedRectangle(57.0, 65.0, 0.25)
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copper-pour(LayerIndex(3), isolate = 0.1) = RoundedRectangle(57.0, 65.0, 0.25)
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ocdb/utils/checks/check-design(self)
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; Set the design name - a directory with this name will be generated under the "designs" directory
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; the board - a Board object
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; [optional] rules - the PCB design rules (if not givn default rules will be used)
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; [optional] vendors - Strings or AuthorizedVendors (if not give default vendors will be used)
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; [optional] quantity - Minimum stock quantity the vendor should carry (if not give default quantity will be used)
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setup-design(
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"jitx-design",
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ocdb/utils/defaults/default-board(ocdb/manufacturers/stackups/jlcpcb-jlc2313, board-shape)
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)
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; Set the schematic sheet size
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set-paper(ANSI-A)
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; Set the top level module (the module to be compile into a schematic and PCB)
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set-main-module(logic-analyzer)
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; Use any helper function from helpers.stanza here
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; run-check-on-design(my-design)
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set-bom-vendors(["JLCPCB"])
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set-bom-design-quantity(10)
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set-bom-columns([
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BOMColumn(BOMFieldDescription, "Comment", 20.0)
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BOMColumn(BOMFieldInsts, "Designator", 30.0)
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BOMColumn(BOMFieldSKU, "LCSC Part Number", 20.0)
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])
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set-export-backend(`kicad)
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;export-cad()
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;export-bom()
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; View the results
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view-design-explorer()
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; view-bom(BOM-STD)
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view-board()
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view-schematic() |