mirror of
https://github.com/gusmanb/logicanalyzer.git
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231 lines
8.7 KiB
Python
231 lines
8.7 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2017 Joel Holdsworth <joel@airwebreathe.org.uk>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 3 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sigrokdecode as srd
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from common.srdhelper import bitpack_lsb
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def disabled_enabled(v):
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return ['Disabled', 'Enabled'][v]
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def output_power(v):
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return '{:+d}dBm'.format([-4, -1, 2, 5][v])
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# Notes on the implementation:
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# - A register's description is an iterable of tuples which contain:
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# The starting bit position, the bit count, the name of a field, and
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# an optional parser which interprets the field's content. Parser are
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# expected to yield a single text string when they exist. Other types
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# of output are passed to Python's .format() routine as is.
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# - Bit fields' width in registers determines the range of indices in
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# table/tuple lookups. Keep the implementation as robust as possible
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# during future maintenance. Avoid Python runtime errors when adjusting
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# the decoder.
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regs = {
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# Register description fields:
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# offset, width, name, parser.
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0: (
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( 3, 12, 'FRAC'),
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(15, 16, 'INT',
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None, lambda v: 'Not Allowed' if v < 23 else None,
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),
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),
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1: (
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( 3, 12, 'MOD'),
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(15, 12, 'Phase'),
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(27, 1, 'Prescalar', lambda v: ('4/5', '8/9',)[v]),
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(28, 1, 'Phase Adjust', lambda v: ('Off', 'On',)[v]),
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),
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2: (
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( 3, 1, 'Counter Reset', disabled_enabled),
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( 4, 1, 'Charge Pump Three-State', disabled_enabled),
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( 5, 1, 'Power-Down', disabled_enabled),
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( 6, 1, 'PD Polarity', lambda v: ('Negative', 'Positive',)[v]),
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( 7, 1, 'LDP', lambda v: ('10ns', '6ns',)[v]),
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( 8, 1, 'LDF', lambda v: ('FRAC-N', 'INT-N',)[v]),
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( 9, 4, 'Charge Pump Current Setting',
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lambda v: '{curr:0.2f}mA @ 5.1kΩ'.format(curr = (
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0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50,
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2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00,
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)[v])),
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(13, 1, 'Double Buffer', disabled_enabled),
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(14, 10, 'R Counter'),
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(24, 1, 'RDIV2', disabled_enabled),
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(25, 1, 'Reference Doubler', disabled_enabled),
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(26, 3, 'MUXOUT',
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lambda v: '{text}'.format(text = (
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'Three-State Output', 'DVdd', 'DGND',
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'R Counter Output', 'N Divider Output',
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'Analog Lock Detect', 'Digital Lock Detect',
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'Reserved',
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)[v])),
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(29, 2, 'Low Noise and Low Spur Modes',
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lambda v: '{text}'.format(text = (
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'Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode',
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)[v])),
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),
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3: (
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( 3, 12, 'Clock Divider'),
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(15, 2, 'Clock Divider Mode',
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lambda v: '{text}'.format(text = (
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'Clock Divider Off', 'Fast Lock Enable',
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'Resync Enable', 'Reserved',
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)[v])),
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(18, 1, 'CSR Enable', disabled_enabled),
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(21, 1, 'Charge Cancellation', disabled_enabled),
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(22, 1, 'ABP', lambda v: ('6ns (FRAC-N)', '3ns (INT-N)',)[v]),
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(23, 1, 'Band Select Clock Mode', lambda v: ('Low', 'High',)[v]),
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),
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4: (
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( 3, 2, 'Output Power', output_power),
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( 5, 1, 'Output Enable', disabled_enabled),
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( 6, 2, 'AUX Output Power', output_power),
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( 8, 1, 'AUX Output Select',
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lambda v: ('Divided Output', 'Fundamental',)[v]),
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( 9, 1, 'AUX Output Enable', disabled_enabled),
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(10, 1, 'MTLD', disabled_enabled),
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(11, 1, 'VCO Power-Down',
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lambda v: 'VCO Powered {ud}'.format(ud = 'Down' if v else 'Up')),
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(12, 8, 'Band Select Clock Divider'),
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(20, 3, 'RF Divider Select', lambda v: '÷{:d}'.format(2 ** v)),
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(23, 1, 'Feedback Select', lambda v: ('Divided', 'Fundamental',)[v]),
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),
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5: (
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(22, 2, 'LD Pin Mode',
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lambda v: '{text}'.format(text = (
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'Low', 'Digital Lock Detect', 'Low', 'High',
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)[v])),
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),
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}
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( ANN_REG, ANN_WARN, ) = range(2)
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class Decoder(srd.Decoder):
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api_version = 3
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id = 'adf435x'
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name = 'ADF435x'
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longname = 'Analog Devices ADF4350/1'
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desc = 'Wideband synthesizer with integrated VCO.'
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license = 'gplv3+'
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inputs = ['spi']
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outputs = []
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tags = ['Clock/timing', 'IC', 'Wireless/RF']
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annotations = (
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# Sent from the host to the chip.
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('write', 'Register write'),
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('warning', "Warnings"),
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)
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annotation_rows = (
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('writes', 'Register writes', (ANN_REG,)),
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('warnings', 'Warnings', (ANN_WARN,)),
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)
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def __init__(self):
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self.reset()
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def reset(self):
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self.bits = []
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def start(self):
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self.out_ann = self.register(srd.OUTPUT_ANN)
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def putg(self, ss, es, cls, data):
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self.put(ss, es, self.out_ann, [ cls, data, ])
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def decode_bits(self, offset, width):
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'''Extract a bit field. Expects LSB input data.'''
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bits = self.bits[offset:][:width]
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ss, es = bits[-1][1], bits[0][2]
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value = bitpack_lsb(bits, 0)
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return ( value, ( ss, es, ))
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def decode_field(self, name, offset, width, parser = None, checker = None):
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'''Interpret a bit field. Emits an annotation.'''
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# Get the register field's content and position.
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val, ( ss, es, ) = self.decode_bits(offset, width)
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# Have the field's content formatted, emit an annotation.
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formatted = parser(val) if parser else '{}'.format(val)
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if formatted is not None:
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text = ['{name}: {val}'.format(name = name, val = formatted)]
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else:
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text = ['{name}'.format(name = name)]
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if text:
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self.putg(ss, es, ANN_REG, text)
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# Have the field's content checked, emit an optional warning.
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warn = checker(val) if checker else None
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if warn:
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text = ['{}'.format(warn)]
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self.putg(ss, es, ANN_WARN, text)
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def decode_word(self, ss, es, bits):
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'''Interpret a 32bit word after accumulation completes.'''
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# SPI transfer content must be exactly one 32bit word.
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count = len(self.bits)
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if count != 32:
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text = [
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'Frame error: Bit count: want 32, got {}'.format(count),
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'Frame error: Bit count',
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'Frame error',
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]
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self.putg(ss, es, ANN_WARN, text)
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return
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# Holding bits in LSB order during interpretation simplifies
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# bit field extraction. And annotation emitting routines expect
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# this reverse order of bits' timestamps.
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self.bits.reverse()
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# Determine which register was accessed.
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reg_addr, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
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text = [
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'Register: {addr}'.format(addr = reg_addr),
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'Reg: {addr}'.format(addr = reg_addr),
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'[{addr}]'.format(addr = reg_addr),
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]
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self.putg(reg_ss, reg_es, ANN_REG, text)
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# Interpret the register's content (when parsers are available).
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field_descs = regs.get(reg_addr, None)
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if not field_descs:
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return
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for field_desc in field_descs:
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parser = None
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checker = None
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if len(field_desc) == 3:
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start, count, name, = field_desc
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elif len(field_desc) == 4:
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start, count, name, parser = field_desc
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elif len(field_desc) == 5:
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start, count, name, parser, checker = field_desc
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else:
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# Unsupported regs{} syntax, programmer's error.
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return
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self.decode_field(name, start, count, parser, checker)
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def decode(self, ss, es, data):
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ptype, _, _ = data
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if ptype == 'TRANSFER':
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# Process accumulated bits after completion of a transfer.
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self.decode_word(ss, es, self.bits)
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self.bits.clear()
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if ptype == 'BITS':
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_, mosi_bits, miso_bits = data
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# Accumulate bits in MSB order as they are seen in SPI frames.
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msb_bits = mosi_bits.copy()
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msb_bits.reverse()
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self.bits.extend(msb_bits)
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