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46 lines
1.9 KiB
Python
46 lines
1.9 KiB
Python
##
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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'''
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This protocol decoder can decode synchronous parallel buses with various
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data bits/channels counts, an (optional) clock line, and an (optional)
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select/enable/reset line.
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Data bits are taken from the decoder's lowest connected input pins. The
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input signal's data lines count need not span the full amount of the
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decoder's maximum supported data lines count. Not connected data lines
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are assumed to be low.
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Example use cases are: Connect D3/D2/D1/D0 (and CLK) to a 4-bit bus.
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Connect D7 and D6 to inspect the two most significant bits of an 8-bit
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bus (and have 8-bit values shown instead of just 2-bit values).
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When provided, the specified clock edge determines when data lines get
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sampled. Without a clock spec, each transition on any of the data lines
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will be shown, which can become busy/noisy depending on the input data.
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Another signal optionally can control the period of time within which
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the data lines' bit pattern gets interpreted. Typical use cases would be
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reset, or select, or enable signals that are related to the bus' data
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communication. This optional signal can also improve synchronization to
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wider payload data which spans several bus cycles (multiplexing).
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'''
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from .pd import Decoder
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