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293 lines
9.2 KiB
Markdown
293 lines
9.2 KiB
Markdown
# Gimletlet
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Gimletlet was designed as a service processor host board for testing interfaces
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to blocks of the proposed Gimlet schematic. Compared to the original Gemini
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Bringup board, Gimletlet makes fewer assumptions about what you'll plug into it.
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It exposes common digital interfaces directly, so you can attach external eval
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or test hardware.
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## Render
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The render above shows the board in its "standard" orientation. We'll refer to
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places on the board using compass directions -- there is a North indicator in
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the northwest corner (just to the left of the UART7 connector).
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## Configuration jumpers
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For the board to work, you will need to have the following jumpers set
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correctly. The normal position is in **bold.**
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- JP1 (northeast corner marked "USE JACK")
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- **Installed**: power input barrel jack is the supply to the 3v3 regulator.
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- Removed: to use the 3v3 regulator you must supply power through the
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eastern pin of JP1, e.g. from a bench supply.
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- JP2 (south of J9/I2C2 marked "USE REG")
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- **Installed**: 3v3 regulator is the power source to the SP and expansion
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connectors. You must provide it with power (see above) for it to be
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useful.
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- Removed: you must provide 3.3V from an off-board source, through any of
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the expansion connectors, the J8 header, or the north pin of JP2.
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- JP3 (east of SP marked "ROM BOOT")
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- Installed: contents of SP flash are ignored. SP boots into ROM bootloader.
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- **Removed**: SP boots image in flash, if a valid image exists, and
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otherwise falls back to ROM bootloader.
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## Program/debug
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J15, in the rough center of the board to the southeast of the SP, is the SWD
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header. This allows programming and debugging the SP firmware, and provides
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trace output and logs through the SWO pin. We suggest using an STLink/V3 here.
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Pin 1 is marked with a V as the southwest corner. This means the red stripe on
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the SWD cable should be oriented to the west, and the key facing south.
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Just to the southeast is SW1, the reset switch for the SP.
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## LEDs
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There are four LEDs on the board, controlled by the SP firmware.
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- D1: PG2
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- D2: PG3
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- D3: PG4
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- D4: PG5
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All are active high -- that is, drive the GPIO high to turn on the LED.
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## PMOD
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PMOD is a loose industry standard originally introduced by Digilent on their
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FPGA boards. It's useful because there are off-the-shelf eval modules available
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for a lot of common parts, and they're always 3.3V, so there's no risk of frying
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anything (assuming you plug it in right). The black rectangular connectors
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around the edge of the board are PMOD connectors. Our PMOD connectors follow one
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of four pinouts, three of which are in the standard and one of which is
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de-facto:
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- SPI: PMOD type 2A pinout, which is an "expanded SPI" pinout carrying a SPI bus
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and two extra I/O lines, which can be used as extra chip selects or as
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interrupt/reset lines. You can also insert SPI type 2 (one-row) PMOD modules
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into the _bottom_ row of pins.
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- UART: PMOD type 3 pinout, which carries one UART with hardware flow control.
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- I2C: PMOD type 6 pinout, which carries one I2C bus plus SMB alert and reset
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lines (which can be repurposed as GPIO if you don't need alert/reset).
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- QuadSPI: so, this was intended to match the pinout on Digilent's PMOD-SF3
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flash module, but row 2 is off by one. However, you can still use that board
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in 1 or 2 I/O mode, just not 4. We'll be making our own attachment with the
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specific flash circuits we're using in Gimlet anyway.
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All pinouts are printed on the board. In each case, the pinout is shown from the
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perspective of someone looking down on the board (as in the photo below); the
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square in each pinout maps to the square copper pad on the connector. We did it
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this way because it simplifies choosing a pin to clip with a logic analyzer.
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Note that in all cases, you can also switch the PMOD connector to any of the
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CPU's alternate functions on the same pin, including using them as basic GPIOs.
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This is up to the firmware.
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Starting at the northwest and moving around the edge of the board, these are the
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PMOD connectors, their routing to SP pins, and the STM32H7 Alternate Function
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number:
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- J14: UART7 (all AF7)
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- RX (data into SP): PE7
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- TX (data from SP): PE8
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- ~RTS (output from SP): PE9
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- ~CTS (input to SP): PE10
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- J2: QSPI
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- CLK: PF10 (AF9)
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- IO0: PF8 (AF10)
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- IO1: PF9 (AF10)
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- IO2: PF7 (AF9)
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- IO3: PF6 (AF9)
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- ~CS: PG6 (AF10)
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- PF4 and PF5 are routed to unused pins on the connector.
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- J9: I2C2
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- SDA: PF0 (AF4)
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- SCL: PF1 (AF4)
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- ~SMBA: PF2 (AF4)
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- ~RESET: PF3 (GPIO)
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- J5: SPI6
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- ~CS: PG8 (AF5)
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- SCK: PG13 (AF5)
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- MOSI: PG14 (AF5)
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- MISO: PG12 (AF5)
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- ~INT: PG11 (GPIO)
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- ~RESET: PG15 (GPIO)
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- J13: USART2 (all AF7)
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- RX (data into SP): PD6
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- TX (data from SP): PD5
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- ~RTS (output from SP): PD4
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- ~CTS (input to SP): PD3
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- J3: SPI3
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- ~CS: PA15 (AF6)
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- SCK: PC10 (AF6)
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- MOSI: PC12 (AF6)
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- MISO: PC11 (AF6)
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- ~INT: PD0 (GPIO)
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- ~RESET: PD1 (GPIO)
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- J12: USART1 (all AF7)
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- RX (data into SP): PB7
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- TX (data from SP): PB6
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- ~RTS (output from SP): PA12
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- ~CTS (input to SP): PA11
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- J10: I2C3
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- SDA: PC9 (AF4)
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- SCL: PA8 (AF4)
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- ~SMBA: PA9 (AF4)
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- ~RESET: PA10 (GPIO)
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- J11: I2C4 (shared with NIC, see below)
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- SDA: PF15 (AF4)
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- SCL: PF14 (AF4)
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- ~SMBA: PF13 (AF4)
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- ~RESET: PG0 (GPIO)
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- J4: SPI4 (shared with NIC, see below)
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- ~CS: PE11 (AF5)
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- SCK: PE12 (AF5)
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- MOSI: PE14 (AF5)
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- MISO: PE13 (AF5)
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- ~INT: PE15 (GPIO)
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- ~RESET: PB10 (GPIO)
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## NIC connector
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The NIC connector is on the west edge of the board, and is intended to connect
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to the management network interface circuit (or other Ethernet devices). It
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provides six groups of signals:
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- RMII, the interface from the SP's Ethernet MAC to a PHY or external switch;
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- SMI/MDIO, the management interface used to control Ethernet PHYs;
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- SPI4 for more complex configuration of external switches;
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- I2C4, just in case;
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- Interrupt and reset lines for the PHY and SPI buses; and
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- A group of unassigned GPIOs.
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Note that SPI4 and I2C4 are shared between PMOD headers and the NIC connector.
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You must choose one or the other, or arrange for them not to conflict (for
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example, our current NIC options don't actually use I2C4, and you could choose
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to use an extra pin on the NIC connector as an additional CS to share SPI4).
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The connector is a Hirose DF9 41-pin. Viewed from the top:
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Pinout:
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1. GND
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2. RMII reference clock - 50MHz while PHY/switch is powered.
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- PA1 AF11
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3. MDC - clock output from SP for SMI interface.
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- PC1 AF11
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4. GND
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5. MDIO - bidirectional SMI data.
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- PA2 AF11
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6. RMII `CRS_DV` - receive strobe for "data valid" on the RMII interface.
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- PA7 AF11
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7. ~IRQ from PHY
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- PC0 GPIO
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8. RMII RXD0 - received data to SP
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- PC4 AF11
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9. ~RESET to PHY
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- PA5 GPIO
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10. RMII RXD1 - received data to SP
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- PC5 AF11
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11. GND
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12. GND
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13. PB0 - GPIO
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14. PB1 - GPIO
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15. PB2 - GPIO
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16. PF11 - GPIO
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17. PF12 - GPIO
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18. GND
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19. 3V3
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20. I2C4 ~SMBA
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- PF13 AF4
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21. 3V3
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22. I2C4 SCL
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- PF14 AF4
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23. 3V3
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24. I2C4 SDA
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- PF15 AF4
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25. GND
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26. GND
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27. SPI4 ~CS (shared with PMOD)
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- PE11 AF5
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28. SPI4 SCK
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- PE12 AF5
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29. SPI4 ~INT (shared with PMOD)
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- PE15 GPIO
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30. SPI4 MISO
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- PE13 AF5
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31. SPI4 ~RESET
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- PB10 GPIO
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32. SPI4 MOSI
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- PE14 AF5
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33. 3V3
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34. GND
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35. 3V3
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36. RMII TXEN - transmit strobe from SP for RMII interface
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- PB11 AF11
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37. 3V3
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38. RMII TXD0 - sent data from SP
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- PB12 AF11
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39. GND
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40. RMII TXD1 - sent data from SP
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- PB13 AF11
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41. GND
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Because the Hirose DF9 is difficult to probe, most of these signals are broken
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out to headers and test points:
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- The RMII and MDC signals have labeled test points near the connector.
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- SPI4 is available on J4.
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- I2C4 is available on J11.
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When sharing SPI4 with the PMOD connector, note that any of the PB/PF signals
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could be reappropriated as an extra chip select for the NIC.
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## Ground points
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Near every off-board connector is a ground point -- a metal loop sticking up out
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of the board on an insulated base. These are intended for the ground clip of an
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oscilloscope probe or logic analyzer.
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Ground is also available on the south row of J7/J8 (see below).
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## Power headers
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In addition to the expansion ports, power and ground are available on two
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headers:
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- J7: north row is 12V (or whatever's coming into the barrel jack), south row is
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GND.
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- J8: north row is 3.3V, south row is GND.
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If you have disconnected JP1, you might choose to provide 5+V through the north
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row of J7. If you have disconnected JP2, you might choose to provide 3.3V
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through the north row of J8.
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## Whatever headers
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There are two "whatever headers" on the board providing GPIO for future use,
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along with 3.3v and ground.
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- J17 exposes PE2-PE6.
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- J18 exposes B14/15 and D8-12.
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All these signals are otherwise unused on the board, so you can appropriate them
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without messing up any of the expansion connectors.
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## Where is the root of trust?
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Gimletlet does not have an on-board root of trust, because at the time it was
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built, it was hard to get the right part from NXP. We plan an updated RoT board
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with a PMOD connector that can be attached to any of the SPI headers.
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