mirror of
https://github.com/oxidecomputer/hw-gimletlet.git
synced 2024-12-11 20:35:37 +00:00
1470 lines
32 KiB
Plaintext
1470 lines
32 KiB
Plaintext
{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.381,
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"copper_line_width": 0.254,
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"copper_text_italic": false,
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"copper_text_size_h": 1.524,
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"copper_text_size_v": 1.524,
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"copper_text_thickness": 0.30479999999999996,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.0,
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"height": 1.0,
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"width": 1.0
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},
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"silk_line_width": 0.127,
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"silk_text_italic": false,
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"silk_text_size_h": 0.762,
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"silk_text_thickness": 0.127,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.15239999999999998
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rules": {
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_via_annular_width": 0.09999999999999999,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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},
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"teardrop_options": [
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{
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"td_onpadsmd": true,
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"td_onviapad": true
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}
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],
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"teardrop_parameters": [
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{
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{
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"td_target_name": "td_rect_shape",
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"td_width_to_size_filter_ratio": 0.9
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{
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"td_target_name": "td_track_end",
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [
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0.0,
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0.1524,
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0.15748,
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0.254,
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0.508
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],
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"via_dimensions": [
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{
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{
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"diameter": 0.254,
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{
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{
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"diameter": 0.4064,
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}
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],
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"zones_allow_external_fillets": false
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"erc": {
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"version": 0
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"power_pin_not_driven": "error",
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}
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{
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"pattern": "/AUX_CMD2_SHIFTED"
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{
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{
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{
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{
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},
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{
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},
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{
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{
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{
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},
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{
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"pattern": "/AUX_I2C_SDA"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_CIPO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_CIPO_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_COPI"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_COPI_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_SCK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_SPI_SCK_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS0_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS1_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS2"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS2_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS3"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS3_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS4"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS4_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS5"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS5_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS6"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS6_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS7"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/AUX_STATUS7_SHIFTED"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_PHY_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_PHY_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_PHY_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_PHY_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_SW_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_SW_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_SW_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT0_SW_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_PHY_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_PHY_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_PHY_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_PHY_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_SW_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_SW_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_SW_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/BaseFX_Termination/PORT1_SW_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/12V"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/1V2_EN"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/1V_EN"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/3V3_FB"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/3V3_PGOOD"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/3V3_SS"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/Power Regulation/PWR_EN"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_CRS_DV"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_REF_CLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_RXD0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_RXD1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_TXD0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_TXD1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/RMII_TX_EN"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII0_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII0_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII0_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII0_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII1_RX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII1_RX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII1_TX_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SGMII1_TX_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SMI_MDC"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SMI_MDIO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SPI_DI"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SPI_DO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/SPI_SCLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX0_RX_FPGA_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX0_RX_FPGA_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX0_TX_FPGA_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX0_TX_FPGA_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX1_RX_FPGA_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX1_RX_FPGA_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX1_TX_FPGA_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX1_TX_FPGA_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/AUX_REFCLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/CDONE"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/GNDPLL"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/SCK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/SDI"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/SDO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/SS"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/VCCPLL"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/aux_controller/~{CRESET}"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/CLK_SQUELCH"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/COMA_MODE"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED0_0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED0_1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED1_0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED1_1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED2_0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED2_1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED3_0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/LED3_1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHYADD2"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHYADD3"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHYADD4"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO10"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO11"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO12"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO13"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO4"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO5"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO8"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_GPIO9"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_REFCLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/PHY_REFCLK_EN"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/RCVRDCLK1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/RCVRDCLK2"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REFCLK_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REFCLK_SEL2"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REF_FILT_A"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REF_REXT_A"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REXT0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/REXT1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/RGMII0_TXCLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/RGMII1_TXCLK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII0_RX_PHY_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII0_RX_PHY_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII0_TX_PHY_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII0_TX_PHY_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII1_RX_PHY_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII1_RX_PHY_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII1_TX_PHY_N"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/SGMII1_TX_PHY_P"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/TCK"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/TDI"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/TDO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/TMS"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/TRST"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/VDD1A"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/VDD25A"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/~{PHY_RST}"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/dual_sgmii_phy/~{RST}"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/3V3A"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/EN_REFCLKO"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/FXSD1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/FXSD2"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/ISET"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/P1LED0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/P1LED1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/P2LED0"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/P2LED1"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/REFCLK_I"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
"pattern": "/ethernet_switch/REFCLK_O"
|
|
},
|
|
{
|
|
"netclass": "Default",
|
|
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