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https://github.com/oxidecomputer/hw-gimletlet.git
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99 lines
2.9 KiB
Plaintext
Executable File
99 lines
2.9 KiB
Plaintext
Executable File
iCE40LP1K-CM49
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VSC 8552 - dual SGMII PHY?
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KSZ8463FRL - media converter? 3 port switch
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LQFP-64_10x10mm_P0.5mm footprint exists
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ice40 rails:
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Bank 0+1 VCCIO
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Bank 2+3 VCCIO (LVDS pairs here)
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SPI VCCIO (unused? check if needed w/ NVCM) - yes, needed
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VPP_FAST - MUST connect to VCCIO_0
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VCC - 1.2V, 6.4 mA MAX (15.7 mA compat)
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VPP_2V5 - 2.5V, 7.7 mA MAX (compat)
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VCCPLL - 1.2V, 1.5 mA MAX (8 mA compat)
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KSZ8463FRL rails:
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VDD_IO - ? V, 98 mA (typical)
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"if VDDIO is 1.8V, use external VDD_L"
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VDD_L - internal or external, connect to VDD_AL, VDDCOL
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VDD_COL - connect to VDD_L
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VDD_AL - connect to VDD_L
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VDD_A3.3 - 3.3V, 51 mA (typical)
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VSC8552 rails:
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VDD25A - 2.5V, 265 mA MAX
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VDD25 - 2.5V, 65 mA MAX
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VDD1 - 1V, 755 mA MAX
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VDD1A - 1V, 265 mA MAX
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input power - 12V, 2A
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Rails:
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12V 2A = 24W
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1.2V ~24 mA
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2.5V >330 mA
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1V ~1A - check the tolerances here, very tight
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Preliminary proposal - buck to 3.3V, linear down to 1.2, 1, 2.5
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might split 1 and 1A for current reasons
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Total Iout for buck - <2A
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TPS82140?
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1V LDO - TLV757P - only option in SOT23 @ 1A @ 1V
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1.2V LDO - TLV700 - cheap SC70 option @ 1.2V
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refclks:
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VSC8552 - 125 or 25 MHz, AC coupled, LVDS
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can be SE with circuit described in datasheet
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KSZ8463FRL - 25 or 50 MHz, XTAL or osc, single-ended CMOS
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ice40 - literally whatever lol
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LMK1C1103 1:3 output buffer? need input but would be good
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18002441111
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power sequencing
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KSZ - recommend all at once, if not, A3.3 and VDDIO have no requirement but come before L (irrelevant)
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vsc - no sequencing requirement but power and clock must be stable before releasing reset
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lp4k - when configuring from NVCM, VCC and VPP2V5 must be up 0.25ms before VCCSPI, but maybe not if between 0.4 and 10 V/ms
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UP and LM both require VCC+VCCPLL to come up before VCCIO
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who's on what rail?
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3.3V - only VDD_A3.3 on KSZ, and all the linear regs
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2.5V - VDD_IO on KSZ, VDD25+VDD25A on VSC, VCCIO+VPP_2V5+VCCIO_SPI(?) on LP4K
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1.2V - VCC+VCCPLL on LP4K
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1.0V - VDD1+VDD1A on VSC8552
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2 mA sink on PG implies Rpu of 1.65k or more
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EN thresholds - 0.9V for TLV700, 1V for TLV757
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.31845374111 = t / RC
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so .32 time constants to rise to 0.9V from 3.3V
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if t = 250 us and R = 10kOhm, C = 78 nF
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if R = 10kOhm and C = 100 nF, t = 318 microseconds or so
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arright there's no sequencing req because the requirements are contradictory.
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3V3 investigation - major point of issue is the SMI lines (shared, DC coupled).
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VIH for CMOS inputs on KSZ is 2.1V @ 3.3V
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redo the pull-up math
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MDIO is push-pull, MDC is sourced from master (STM32) - check if VSC can handle it
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VSC is max 3.3V, so should be fine - MDC is explicitly marked 3V tolerant
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STM32 i/o VIH is 2.31V min (CMOS) at 3.3V. i call it good.
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new target - 0.9987 in
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left to right - 30, 31, 20, 21, 10, 11, 00, 01
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left to right - 5, 4, 11, 10, 9, 12, 8, 13, clk2, clk1 (0 and 1 whereever)
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aux - bias the receiver? |