AllSpiceMirrors/jellyfish-powersupply
0
Fork 0
mirror of https://gitlab.com/hyperglitch/jellyfish.git synced 2025-04-17 12:38:56 +00:00
Files Issues Releases Activity

Commit Graph

  • 4eb6d5e6e6 fix licensing info, make everything reuse compliant main Igor Brkic 2025-04-09 12:53:45 +0200
  • ba9c5703e6 add cube mx file Igor Brkic 2025-04-08 22:34:15 +0200
  • ce2c327413 add timer based ADC sampling, add scpi interface Igor Brkic 2025-04-08 22:32:05 +0200
  • 3a9de68627 code refactoring for better organization Igor Brkic 2025-04-03 12:26:21 +0200
  • 8281e091f3 rev 2 production files Igor Brkic 2025-04-01 12:16:41 +0200
  • 17fd009df0 prepare script: added export for all fab files Igor Brkic 2025-03-31 01:26:45 +0200
  • 61466fddea adjust text on fab layer Igor Brkic 2025-03-31 01:08:16 +0200
  • 7cd9bacb92 update BOM exclusions Igor Brkic 2025-03-31 00:26:49 +0200
  • 9cb6c4631e implement all changes for 2.0 revision Igor Brkic 2025-03-30 23:59:55 +0200
  • 90fe822d7c add licenses Igor Brkic 2025-03-09 01:00:16 +0100
  • d3b89c87b1 add firmware code Igor Brkic 2025-03-09 00:59:24 +0100
  • f6628e778b add verilog files Igor Brkic 2025-03-09 00:37:34 +0100
  • b6287c72da add annotations for the changes to the schematic Igor Brkic 2025-03-06 15:13:07 +0100
  • 63efd9a6b0 PCB done for first prototype, production files ready Igor Brkic 2024-07-13 00:35:20 +0200
  • b7ade1a23e routing done Igor Brkic 2024-07-06 19:57:39 +0200
  • 21a3dedb0c routing done 90%, board layout defined Igor Brkic 2024-06-22 18:39:47 +0200
  • ce239e3af6 add fw+gw placeholders Igor Brkic 2024-04-12 23:32:38 +0200
  • 3efa6c6a71 add nlnet info to readme Igor Brkic 2024-04-12 23:31:37 +0200
  • acc8a69ef6 add pdf schematic Igor Brkic 2024-04-11 11:42:21 +0200
  • dcf8914720 ina supply filtering, small changes Igor Brkic 2024-04-11 11:40:47 +0200
  • 6a8b4dfa41 ignore temporary fab files Igor Brkic 2024-04-11 11:39:50 +0200
  • 332ec4c8a5 production folder cleanup Igor Brkic 2024-04-11 11:38:44 +0200
  • a323325e5d add licensing info according to REUSE Igor Brkic 2024-04-10 12:19:16 +0200
  • e9e1c3984c remove backup files Igor Brkic 2024-04-10 12:04:31 +0200
  • 2976d52776 full schematic first commit Igor Brkic 2024-04-10 11:53:27 +0200
  • 69520646c1 add output stage simulation (LTSpice) Igor Brkic 2023-11-06 15:17:36 +0100
  • 7964e0d7e1 license update Igor Brkic 2023-11-06 15:15:33 +0100
  • ce869259f3 initial testing revision of the output stage Igor Brkic 2023-11-06 15:12:31 +0100