# SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com> # SPDX-License-Identifier: GPL-3.0-or-later PROJ = jellyfishopp DEVICE = hx1k BUILDDIR = build SRCDIR = src TESTDIR = test # Default board #BOARD ?= jellyfish # Board-specific settings ifeq ($(BOARD), jellyfish) PIN_DEF = jellyfish.pcf PACKAGE = tq144 else ifeq ($(BOARD), evb) PIN_DEF = ice40hx1k-evb.pcf PACKAGE = vq100 else $(error Invalid BOARD specified. Choose 'jellyfish' or 'evb') endif VERILOG_FILES = $(wildcard $(SRCDIR)/*.v) TESTBENCH_FILES = $(wildcard $(TESTDIR)/*.sv) TESTBENCH_TARGETS = $(patsubst $(TESTDIR)/%.sv,$(BUILDDIR)/%.out,$(TESTBENCH_FILES)) all: $(BUILDDIR)/$(PROJ).rpt $(BUILDDIR)/$(PROJ).bin $(BUILDDIR): mkdir -p $(BUILDDIR) $(BUILDDIR)/%.json: $(VERILOG_FILES) | $(BUILDDIR) yosys -p 'read_verilog -lib +/ice40/cells_sim.v; hierarchy -check -top top; synth_ice40 -top top -json $@' $(VERILOG_FILES) $(BUILDDIR)/%.asc: $(BUILDDIR)/%.json nextpnr-ice40 -q --$(DEVICE) --pcf $(PIN_DEF) --asc $@ --package $(PACKAGE) --json $^ $(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc icepack $< $@ $(BUILDDIR)/%.rpt: $(BUILDDIR)/%.asc icetime -d $(DEVICE) -mtr $@ $< prog: $(BUILDDIR)/$(PROJ).bin # -S to copy to SRAM iceprog -d i:0x0403:0x6010 -I B -S $< prog-flash: $(BUILDDIR)/$(PROJ).bin # -S to copy to SRAM iceprog -d i:0x0403:0x6010 -I B $< # Pattern rule for running a specific testbench $(BUILDDIR)/%.out: $(TESTDIR)/%.v $(VERILOG_FILES) | $(BUILDDIR) @echo "Running testbench $<..." iverilog -g2012 -o $@ -DBUILDDIR=\"$(BUILDDIR)\" $(VERILOG_FILES) $< vvp $@ # Rule for running all testbenches test: $(TESTBENCH_TARGETS) # Rule for running a specific testbench by name test-%: | $(BUILDDIR) @echo "Running specific testbench $*..." iverilog -g2012 -o $(BUILDDIR)/$*.out $(VERILOG_FILES) $(TESTDIR)/$*.sv test/_modules.sv vvp $(BUILDDIR)/$*.out # try to synthesize one module synth-%: $(BUILDDIR) yosys -p 'hierarchy -check -top top; synth_ice40 -top top -json build/synth-$*.json' src/spi_dac.v synth/$*_top.v clean: rm -rf $(BUILDDIR) .PHONY: all prog clean