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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
353 lines
13 KiB
Verilog
353 lines
13 KiB
Verilog
// SPDX-FileCopyrightText: 2021 Shawn Hymel
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// SPDX-License-Identifier: 0BSD
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// Verilog code written by Shawn Hymel based on the Clifford E. Cummings
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// paper http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
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`default_nettype none
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module async_fifo #(
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// Parameters
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parameter DATA_SIZE = 8, // Number of data bits
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parameter ADDR_SIZE = 4 // Number of bits for address
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) (
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// Inputs
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input [DATA_SIZE-1:0] w_data, // Data to be written to FIFO
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input w_en, // Write data and increment addr.
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input w_clk, // Write domain clock
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input w_rst, // Write domain reset
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input r_en, // Read data and increment addr.
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input r_clk, // Read domain clock
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input r_rst, // Read domain reset
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// Outputs
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output w_full, // Flag: 1 if FIFO is full
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output w_almost_full, // Flag: 1 if FIFO is almost full
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output reg [DATA_SIZE-1:0] r_data, // Data to be read from FIFO
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output r_empty, // Flag: 1 if FIFO is empty
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output reg dbgled
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);
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// Constants
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localparam FIFO_DEPTH = (1 << ADDR_SIZE);
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// Internal signals
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wire [ADDR_SIZE-1:0] w_addr;
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wire [ADDR_SIZE:0] w_gray;
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wire [ADDR_SIZE-1:0] r_addr;
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wire [ADDR_SIZE:0] r_gray;
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// Internal storage elements
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reg [ADDR_SIZE:0] w_syn_r_gray;
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reg [ADDR_SIZE:0] w_syn_r_gray_pipe;
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reg [ADDR_SIZE:0] r_syn_w_gray;
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reg [ADDR_SIZE:0] r_syn_w_gray_pipe;
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// Declare memory
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reg [DATA_SIZE-1:0] mem [0:FIFO_DEPTH-1];
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initial mem[0] <= 255;// fill the first byte to let Yosys infer to BRAM.
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//--------------------------------------------------------------------------
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// Dual-port memory (should be inferred as block RAM)
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// Write data logic for dual-port memory (separate write clock)
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// Do not write if FIFO is full!
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always @ (posedge w_clk) begin
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if (w_en & ~w_full) begin
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dbgled <= ~dbgled;
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mem[w_addr] <= w_data;
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end
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end
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// Read data logic for dual-port memory (separate read clock)
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// Do not read if FIFO is empty!
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always @ (posedge r_clk) begin
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if (r_en & ~r_empty) begin
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r_data <= mem[r_addr];
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end
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end
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//--------------------------------------------------------------------------
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// Synchronizer logic
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// Pass read-domain Gray code pointer to write domain
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always @ (posedge w_clk or posedge w_rst) begin
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if (w_rst == 1'b1) begin
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w_syn_r_gray_pipe <= 0;
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w_syn_r_gray <= 0;
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end else begin
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w_syn_r_gray_pipe <= r_gray;
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w_syn_r_gray <= w_syn_r_gray_pipe;
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end
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end
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// Pass write-domain Gray code pointer to read domain
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always @ (posedge r_clk or posedge r_rst) begin
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if (r_rst == 1'b1) begin
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r_syn_w_gray_pipe <= 0;
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r_syn_w_gray <= 0;
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end else begin
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r_syn_w_gray_pipe <= w_gray;
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r_syn_w_gray <= r_syn_w_gray_pipe;
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end
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end
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//--------------------------------------------------------------------------
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// Instantiate incrementer and full/empty checker modules
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// Write address increment and full check module
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w_ptr_full #(.ADDR_SIZE(ADDR_SIZE)) w_ptr_full (
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.w_syn_r_gray(w_syn_r_gray),
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.w_inc(w_en),
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.w_clk(w_clk),
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.w_rst(w_rst),
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.w_addr(w_addr),
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.w_gray(w_gray),
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.w_full(w_full),
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.w_almost_full(w_almost_full)
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);
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// Read address increment and empty check module
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r_ptr_empty #(.ADDR_SIZE(ADDR_SIZE)) r_ptr_empty (
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.r_syn_w_gray(r_syn_w_gray),
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.r_inc(r_en),
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.r_clk(r_clk),
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.r_rst(r_rst),
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.r_addr(r_addr),
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.r_gray(r_gray),
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.r_empty(r_empty)
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);
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endmodule
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// Increment read address and check if FIFO is empty
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module r_ptr_empty #(
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// Parameters
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parameter ADDR_SIZE = 4 // Number of bits for address
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) (
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// Inputs
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input [ADDR_SIZE:0] r_syn_w_gray, // Synced write Gray pointer
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input r_inc, // 1 to increment address
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input r_clk, // Read domain clock
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input r_rst, // Read domain reset
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// Outputs
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output [ADDR_SIZE-1:0] r_addr, // Mem address to read from
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output reg [ADDR_SIZE:0] r_gray, // Gray address with +1 MSb
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output reg r_empty // 1 if FIFO is empty
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);
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// Internal signals
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wire [ADDR_SIZE:0] r_gray_next; // Gray code version of address
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wire [ADDR_SIZE:0] r_bin_next; // Binary version of address
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wire r_empty_val; // FIFO is empty
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// Internal storage elements
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reg [ADDR_SIZE:0] r_bin; // Registered binary address
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// Drop extra most significant bit (MSb) for addressing into memory
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assign r_addr = r_bin[ADDR_SIZE-1:0];
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// Be ready with next (incremented) address (if inc set and not empty)
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assign r_bin_next = r_bin + (r_inc & ~r_empty);
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// Convert next binary address to Gray code value
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assign r_gray_next = (r_bin_next >> 1) ^ r_bin_next;
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// If the synced write Gray code is equal to the current read Gray code,
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// then the pointers have caught up to each other and the FIFO is empty
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assign r_empty_val = (r_gray_next == r_syn_w_gray);
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// Register the binary and Gray code pointers in the read clock domain
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always @ (posedge r_clk or posedge r_rst) begin
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if (r_rst == 1'b1) begin
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r_bin <= 0;
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r_gray <= 0;
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end else begin
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r_bin <= r_bin_next;
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r_gray <= r_gray_next;
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end
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end
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// Register the empty flag
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always @ (posedge r_clk or posedge r_rst) begin
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if (r_rst == 1'b1) begin
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r_empty <= 1'b1;
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end else begin
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r_empty <= r_empty_val;
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end
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end
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endmodule
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// Increment write address and check if FIFO is full
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module w_ptr_full #(
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// Parameters
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parameter ADDR_SIZE = 4 // Number of bits for address
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) (
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// Inputs
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input [ADDR_SIZE:0] w_syn_r_gray, // Synced read Gray pointer
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input w_inc, // 1 to increment address
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input w_clk, // Write domain clock
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input w_rst, // Write domain reset
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// Outputs
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output [ADDR_SIZE-1:0] w_addr, // Mem address to write to
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output reg [ADDR_SIZE:0] w_gray, // Gray adress with +1 MSb
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output reg w_full, // 1 if FIFO is full
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output reg w_almost_full // 1 if FIFO is almost full
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);
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// Internal signals
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wire [ADDR_SIZE:0] w_gray_next; // Gray code version of address
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wire [ADDR_SIZE:0] w_bin_next; // Binary version of address
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wire w_full_val; // FIFO is full
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wire [ADDR_SIZE:0] w_almost_full_val8;
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wire [ADDR_SIZE:0] w_almost_full_val7;
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wire [ADDR_SIZE:0] w_almost_full_val6;
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wire [ADDR_SIZE:0] w_almost_full_val5;
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wire [ADDR_SIZE:0] w_almost_full_val4;
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wire [ADDR_SIZE:0] w_almost_full_val3;
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wire [ADDR_SIZE:0] w_almost_full_val2;
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wire [ADDR_SIZE:0] w_almost_full_val1;
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// Internal storage elements
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reg [ADDR_SIZE:0] w_bin; // Registered binary address
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// Drop extra most significant bit (MSb) for addressing into memory
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assign w_addr = w_bin[ADDR_SIZE-1:0];
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// Be ready with next (incremented) address (if inc set and not full)
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assign w_bin_next = w_bin + (w_inc & ~w_full);
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// Convert next binary address to Gray code value
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assign w_gray_next = (w_bin_next >> 1) ^ w_bin_next;
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// with this approach for making the "almost full" flag, the flag is
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// active only when the available space is frame_size-1. In order not to
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// complicate the code too much, the frame size is fixed to 8 and there
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// are conditions for each of the lower values of the frame size so that
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// the flag is kept active for all of them.
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wire [ADDR_SIZE:0] w_bin_plus_8 = w_bin + 8;
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wire [ADDR_SIZE:0] w_gray_plus_8 = (w_bin_plus_8 >> 1) ^ w_bin_plus_8;
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wire [ADDR_SIZE:0] w_bin_plus_7 = w_bin + 7;
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wire [ADDR_SIZE:0] w_gray_plus_7 = (w_bin_plus_7 >> 1) ^ w_bin_plus_7;
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wire [ADDR_SIZE:0] w_bin_plus_6 = w_bin + 6;
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wire [ADDR_SIZE:0] w_gray_plus_6 = (w_bin_plus_6 >> 1) ^ w_bin_plus_6;
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wire [ADDR_SIZE:0] w_bin_plus_5 = w_bin + 5;
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wire [ADDR_SIZE:0] w_gray_plus_5 = (w_bin_plus_5 >> 1) ^ w_bin_plus_5;
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wire [ADDR_SIZE:0] w_bin_plus_4 = w_bin + 4;
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wire [ADDR_SIZE:0] w_gray_plus_4 = (w_bin_plus_4 >> 1) ^ w_bin_plus_4;
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wire [ADDR_SIZE:0] w_bin_plus_3 = w_bin + 3;
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wire [ADDR_SIZE:0] w_gray_plus_3 = (w_bin_plus_3 >> 1) ^ w_bin_plus_3;
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wire [ADDR_SIZE:0] w_bin_plus_2 = w_bin + 2;
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wire [ADDR_SIZE:0] w_gray_plus_2 = (w_bin_plus_2 >> 1) ^ w_bin_plus_2;
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wire [ADDR_SIZE:0] w_bin_plus_1 = w_bin + 1;
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wire [ADDR_SIZE:0] w_gray_plus_1 = (w_bin_plus_1 >> 1) ^ w_bin_plus_1;
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// Compare write Gray code to synced read Gray code to see if FIFO is full
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// If: extra MSb of read and write Gray codes are not equal AND
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// 2nd MSb of read and write Gray codes are not equal AND
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// the rest of the bits are equal
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// Then: address pointers are same with write pointer ahead by 2^ADDR_SIZE
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// elements (i.e. wrapped around), so FIFO is full.
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assign w_full_val = ((w_gray_next[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_next[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_next[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0]));
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assign w_almost_full_val8 = (
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(w_gray_plus_8[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_8[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_8[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val7 = (
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(w_gray_plus_7[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_7[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_7[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val6 = (
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(w_gray_plus_6[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_6[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_6[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val5 = (
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(w_gray_plus_5[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_5[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_5[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val4 = (
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(w_gray_plus_4[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_4[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_4[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val3 = (
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(w_gray_plus_3[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_3[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_3[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val2 = (
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(w_gray_plus_2[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_2[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_2[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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assign w_almost_full_val1 = (
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(w_gray_plus_1[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
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(w_gray_plus_1[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
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(w_gray_plus_1[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0])
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);
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// Register the binary and Gray code pointers in the write clock domain
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always @ (posedge w_clk or posedge w_rst) begin
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if (w_rst == 1'b1) begin
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w_bin <= 0;
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w_gray <= 0;
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end else begin
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w_bin <= w_bin_next;
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w_gray <= w_gray_next;
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end
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end
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// Register the full flag
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always @ (posedge w_clk or posedge w_rst) begin
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if (w_rst == 1'b1) begin
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w_full <= 1'b0;
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w_almost_full <= 1'b0;
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end else begin
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w_full <= w_full_val;
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w_almost_full <= w_almost_full_val8 | w_almost_full_val7 | w_almost_full_val6 | w_almost_full_val5 | w_almost_full_val4 | w_almost_full_val3 | w_almost_full_val2 | w_almost_full_val1 | w_full_val;
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end
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end
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endmodule
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