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30 lines
952 B
Verilog
30 lines
952 B
Verilog
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module demux8
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(
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input [2:0] i_sel,
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input i_in,
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input i_en,
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output reg o_out0,
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output reg o_out1,
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output reg o_out2,
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output reg o_out3,
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output reg o_out4,
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output reg o_out5,
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output reg o_out6,
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output reg o_out7
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);
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assign o_out0 = !i_sel[2] & !i_sel[1] & !i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out1 = !i_sel[2] & !i_sel[1] & i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out2 = !i_sel[2] & i_sel[1] & !i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out3 = !i_sel[2] & i_sel[1] & i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out4 = i_sel[2] & !i_sel[1] & !i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out5 = i_sel[2] & !i_sel[1] & i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out6 = i_sel[2] & i_sel[1] & !i_sel[0] & i_en ? i_in : 1'b0;
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assign o_out7 = i_sel[2] & i_sel[1] & i_sel[0] & i_en ? i_in : 1'b0;
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endmodule
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