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53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module latch #(
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parameter integer DURATION = 1000000
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)(
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input i_clk,
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input i_rst,
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input i_trigger,
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output reg o_signal
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);
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reg [$clog2(DURATION)-1:0] duration_counter = 0;
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localparam [1:0] STATE_IDLE = 2'd0;
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localparam [1:0] STATE_LATCH = 2'd1;
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reg [1:0] state = STATE_IDLE;
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always @(posedge i_clk or posedge i_rst) begin
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if (i_rst) begin
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state <= STATE_IDLE;
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duration_counter <= 0;
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o_signal <= 1'b0;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (i_trigger == 1'b1) begin
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state <= STATE_LATCH;
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duration_counter <= 0;
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o_signal <= 1'b1;
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end
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end
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STATE_LATCH: begin
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duration_counter <= duration_counter + 1;
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if (duration_counter == DURATION-1) begin
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state <= STATE_IDLE;
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o_signal <= 1'b0;
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end
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end
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default: begin
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state <= STATE_IDLE;
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end
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endcase
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end
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end
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endmodule
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