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50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module mavg #(
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parameter WIDTH = 16,
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parameter DEPTH = 16
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)(
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input wire clk,
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input wire rst,
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input wire trig, // trigger signal
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input wire signed [WIDTH-1:0] in_sample,
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output reg signed [WIDTH-1:0] out_avg
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);
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// Internal parameters
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localparam SUM_WIDTH = WIDTH + $clog2(DEPTH);
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// Circular buffer to hold last 16 samples
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reg signed [WIDTH-1:0] buffer [0:DEPTH-1];
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reg [3:0] ptr; // buffer index 0..15
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// Running sum of the DEPTH samples
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reg signed [SUM_WIDTH-1:0] sum;
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integer i;
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// Sequential logic: sample and compute when triggered
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always @(posedge clk) begin
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if (rst) begin
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sum <= 0;
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ptr <= 0;
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out_avg <= 0;
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for (i = 0; i < DEPTH; i = i + 1)
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buffer[i] <= 0;
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end else if (trig) begin
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// Update running sum: remove oldest, add new
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sum <= sum - buffer[ptr] + in_sample;
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// Store new sample
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buffer[ptr] <= in_sample;
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// Advance pointer with wrap-around
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ptr <= ptr + 1;
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// Compute and register moving average
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out_avg <= sum >> 4;
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end
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// if not triggered, retain previous state
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end
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endmodule
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