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41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module synchronizer(
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input wire async_signal, // Fast asynchronous input signal
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input wire clk, // FPGA clock (slower clock domain)
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output reg rising_edge // Rising edge detected
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);
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// Registers for edge detection
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reg async_prev; // Previous state of async_signal
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reg async_rising; // Rising edge detected in async domain
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// Process for edge detection (single-edge sensitive)
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always @(posedge async_signal) begin
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async_rising <= 1'b1; // Detect rising edge
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end
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// Update previous state of async_signal in a separate block
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always @(posedge clk) begin
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async_prev <= async_signal; // Track previous value in async domain
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end
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// Synchronize rising and falling edges to FPGA clock
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reg sync_rising_0, sync_rising_1;
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always @(posedge clk) begin
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// Synchronize rising edge
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sync_rising_0 <= async_rising;
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sync_rising_1 <= sync_rising_0;
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if (sync_rising_1) begin
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rising_edge <= 1'b1;
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async_rising <= 1'b0; // Clear rising edge latch
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end else begin
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rising_edge <= 1'b0;
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end
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end
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endmodule
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