jellyfish-powersupply/gw/test/_module_sb_io.sv

// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
// SPDX-License-Identifier: GPL-3.0-or-later

module SB_IO #(
    parameter [5:0] PIN_TYPE = 6'b000000, // Not used in mock
    parameter PULLUP = 1'b0               // Optional pull-up
) (
    inout wire PACKAGE_PIN,
    input wire OUTPUT_ENABLE,
    input wire D_OUT_0,
    input wire D_OUT_1, // Ignored in this model
    output wire D_IN_0,
    output wire D_IN_1
);

    // Internal tri-state net for simulating bidirectional pin
    wire pin_out;
    wire pin_in;

    // Simulate FPGA output behavior: drive the pin only when OE is active
    assign pin_out = OUTPUT_ENABLE ? D_OUT_0 : 1'bz;
    assign PACKAGE_PIN = pin_out;

    // Simulate pull-up when pin is undriven and pull-up is enabled
    wire pullup_effect = (PACKAGE_PIN === 1'bz && PULLUP) ? 1'b1 : PACKAGE_PIN;

    // Simulate input behavior (what the FPGA would "see")
    assign pin_in = (!OUTPUT_ENABLE) ? pullup_effect : 1'bz;

    // Input wires reflect PACKAGE_PIN when not driving
    assign D_IN_0 = pin_in;
    assign D_IN_1 = pin_in; // Same as D_IN_0, simplified for mock

endmodule