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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
40 lines
908 B
Systemverilog
40 lines
908 B
Systemverilog
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module SB_RAM40_4K #(
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parameter WRITE_MODE = 1,
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parameter READ_MODE = 0
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)(
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input wire [15:0] WDATA,
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input wire [11:0] WADDR,
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input wire WCLK,
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input wire WCLKE,
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input wire WE,
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input wire [11:0] RADDR,
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output reg [15:0] RDATA,
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input wire RCLK,
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input wire RCLKE,
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input wire RE
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);
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// iCE40 BRAM has 4K bits; we're using 16-bit wide words = 256 entries
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reg [15:0] mem [0:255];
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// Write logic
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always @(posedge WCLK) begin
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if (WCLKE && WE) begin
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mem[WADDR[7:0]] <= WDATA; // Only 256 words
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end
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end
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// Read logic
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always @(posedge RCLK) begin
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if (RCLKE && RE) begin
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RDATA <= mem[RADDR[7:0]];
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end
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end
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endmodule
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