jellyfish-powersupply/gw/test/adc_ctrl_tb.sv

`timescale 1ns/1ps

// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
// SPDX-License-Identifier: GPL-3.0-or-later

//TB_DEPS: src/adc_ctrl.v

module adc_ctrl_tb;

  reg i_rst;
  reg i_clk;
  wire o_ncs1;
  wire o_ncs2;
  wire o_sdi;
  reg i_sdo0;
  reg i_sdo1;
  reg i_sdo2;
  reg i_sdo3;
  reg i_sdo4;
  reg i_sdo5;
  reg i_sdo6;
  reg i_sdo7;
  wire o_sck;
  wire o_nrst;
  wire o_convst;
  reg i_rdy1;
  reg i_rdy2;

  reg ext_gpio_0 = 1'b0;
  reg ext_gpio_1 = 1'b1;
  reg ext_gpio_2 = 1'b0;
  reg ext_gpio_3 = 1'b0;
  reg ext_gpio_4 = 1'b1;

  reg i_trigger = 0;
  wire [15:0] o_data;
  wire o_data_ready;

  reg [2:0] i_range_user = 3'd6;
  wire [2:0] o_range_select;
  reg i_data_fifo_full = 0;

  adc_ctrl adc (
    .i_rst(i_rst),
    .i_clk(i_clk),

    .o_ncs1(o_ncs1),
    .o_ncs2(o_ncs2),
    .o_sdi(o_sdi),
    .i_sdo0(i_sdo0),
    .i_sdo1(i_sdo1),
    .i_sdo2(i_sdo2),
    .i_sdo3(i_sdo3),
    .i_sdo4(i_sdo4),
    .i_sdo5(i_sdo5),
    .i_sdo6(i_sdo6),
    .i_sdo7(i_sdo7),
    .o_sck(o_sck),
    .o_nrst(o_nrst),

    .o_convst(o_convst),
    .i_rdy1(i_rdy1),
    .i_rdy2(i_rdy2),

    .i_trigger(i_trigger),
    .o_data(o_data),
    .o_data_ready(o_data_ready),
    .i_data_fifo_full(i_data_fifo_full),

    .ext_gpio({ext_gpio_0, ext_gpio_1, ext_gpio_2, ext_gpio_3, ext_gpio_4}),

    .i_range_user(i_range_user),
    .o_range_select(o_range_select)
  );

  // generate a clock
  initial begin
    i_clk = 0;
    forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
  end

  localparam DATA_A0 = 16'hffe2;
  localparam DATA_A1 = 16'ha126;
  localparam DATA_B0 = 16'h1234;
  localparam DATA_B1 = 16'h2235;

  // generate a test sequence
  initial begin
    i_rst = 1;  // reset the number blinker
    i_rdy1 = 0;
    i_rdy2 = 0;

    i_sdo0 = 1'b0;
    i_sdo1 = 1'b0;
    i_sdo2 = 1'b0;
    i_sdo3 = 1'b0;
    i_sdo4 = 1'b0;
    i_sdo5 = 1'b0;
    i_sdo6 = 1'b0;
    i_sdo7 = 1'b0;

    #10;
    i_rst = 0;  // release reset
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end

    // new sample
    #100;
    i_trigger = 1;
    #10
    i_trigger = 0;
    #20
    i_rdy1 = 1;
    i_rdy2 = 1;
    #10
    i_rdy1 = 0;
    i_rdy2 = 0;

    #2;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_A0[i];
      i_sdo4 = DATA_A1[i];
      #20;
    end

    #10;
    for(int i=15; i>=0; i--) begin
      i_sdo0 = DATA_B0[i];
      i_sdo4 = DATA_B1[i];
      #20;
    end



    #2000;  // allow the simulation to run for some time

    $finish;
  end

  initial begin
    $dumpfile("build/adc_ctrl_tb.vcd");
    $dumpvars(0, adc_ctrl_tb);
  end

endmodule