jellyfish-powersupply/gw/test/async_fifo_tb.sv

// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
// SPDX-License-Identifier: GPL-3.0-or-later

// Define timescale
`timescale 1 us / 10 ps

//TB_DEPS: src/async_fifo.v

module async_fifo_tb();

    // Settings
    localparam  DATA_SIZE = 16;
    localparam  ADDR_SIZE = 4;

    // Internal signals
    wire    [DATA_SIZE-1:0]     r_data;
    wire                        r_empty;
    wire                        w_full;
    wire                        w_almost_full;

    // Internal storage elements
    reg                         r_en = 0;
    reg                         r_clk = 0;
    reg                         r_rst = 0;
    reg     [DATA_SIZE-1:0]     w_data;
    reg                         w_en = 0;
    reg                         w_clk = 0;
    reg                         w_rst = 0;

    // Variables
    integer                     i;

    localparam DURATION = 8; // 8us

    // Generate read clock signal (about 12 MHz)
    always begin
        #0.04167
        r_clk = ~r_clk;
    end

    // Generate write clock signal (5 MHz)
    always begin
        #0.1
        w_clk = ~w_clk;
    end

    // Instantiate FIFO
    async_fifo #(
        .DATA_SIZE(DATA_SIZE),
        .ADDR_SIZE(ADDR_SIZE)
    ) uut (
        .w_data(w_data),
        .w_en(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .r_en(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .w_full(w_full),
        .w_almost_full(w_almost_full),
        .r_data(r_data),
        .r_empty(r_empty)
    );

    // Test control: write and read data to/from FIFO
    initial begin

        // Pulse resets high to initialize memory and counters
        #0.1
        w_rst = 1;
        r_rst = 1;
        #0.01
        w_rst = 0;
        r_rst = 0;

        // Write some data to the FIFO
        for (i = 0; i < 14; i = i + 1) begin
            #0.2
            w_data = i;
            w_en = 1'b1;
        end
        #0.2
        w_en = 1'b0;

        // Try to read more than what's in the FIFO
        for (i = 0; i < 6; i = i + 1) begin
            #0.08334
            r_en = 1'b1;
        end
        #0.08334
        r_en = 1'b0;

        // Fill up FIFO (and then some)
        for (i = 0; i < 8; i = i + 1) begin
            #0.2
            w_en = 1'b1;
            w_data = i;
        end
        #0.2
        w_en = 1'b0;

        // Read everything in the FIFO (and then some)
        for (i = 0; i < 18; i = i + 1) begin
            #0.08334
            r_en = 1'b1;
        end
        #0.08334
        r_en = 1'b0;

        $finish;
    end

    // Run simulation
    initial begin

        // Create simulation output file 
        $dumpfile("build/async_fifo_tb.vcd");
        $dumpvars(0, async_fifo_tb);

    end

endmodule