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jellyfish-powersupply/gw/test/auto_range_tb.sv

65 lines
1003 B
Systemverilog

`timescale 1ns/1ps
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
// SPDX-License-Identifier: GPL-3.0-or-later
//TB_DEPS: src/auto_range.v
module auto_range_tb;
reg i_rst;
reg i_clk;
reg i_trigger;
reg signed [15:0] isense;
wire [2:0] range_sel;
auto_range auto_range (
.i_clk(i_clk),
.i_rst(i_rst),
.i_trigger(i_trigger),
.isense(isense),
.range_sel(range_sel)
);
// generate a clock
initial begin
i_clk = 0;
forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
end
initial begin
i_rst = 1;
isense = 0;
i_trigger = 0;
#10;
i_rst = 0;
#10;
isense = -200;
i_trigger = 1;
#10;
i_trigger = 0;
#50;
isense = -1048;
i_trigger = 1;
#10;
i_trigger = 0;
#50;
isense = -1048;
i_trigger = 1;
#10;
i_trigger = 0;
#100;
$finish;
end
initial begin
$dumpfile("build/auto_range_tb.vcd");
$dumpvars(0, auto_range_tb);
end
endmodule