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65 lines
1003 B
Systemverilog
65 lines
1003 B
Systemverilog
`timescale 1ns/1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/auto_range.v
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module auto_range_tb;
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reg i_rst;
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reg i_clk;
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reg i_trigger;
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reg signed [15:0] isense;
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wire [2:0] range_sel;
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auto_range auto_range (
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.i_clk(i_clk),
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.i_rst(i_rst),
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.i_trigger(i_trigger),
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.isense(isense),
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.range_sel(range_sel)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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initial begin
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i_rst = 1;
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isense = 0;
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i_trigger = 0;
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#10;
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i_rst = 0;
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#10;
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isense = -200;
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i_trigger = 1;
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#10;
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i_trigger = 0;
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#50;
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isense = -1048;
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i_trigger = 1;
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#10;
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i_trigger = 0;
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#50;
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isense = -1048;
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i_trigger = 1;
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#10;
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i_trigger = 0;
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#100;
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$finish;
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end
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initial begin
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$dumpfile("build/auto_range_tb.vcd");
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$dumpvars(0, auto_range_tb);
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end
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endmodule
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