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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
66 lines
1.3 KiB
Systemverilog
66 lines
1.3 KiB
Systemverilog
`timescale 1ns / 1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/clock_divider.v
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module clock_divider_tb;
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reg i_rst;
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reg i_clk;
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wire o_clk16, o_clk4, o_clk2, o_clk1;
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// instantiate the clock divider with a divisor of 64
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clock_divider #(.DIVISOR(16)) cd16 (
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.i_rst(i_rst),
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.i_clk(i_clk),
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.o_clk(o_clk16)
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);
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// instantiate the clock divider with a divisor of 4
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clock_divider #(.DIVISOR(4)) cd4 (
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.i_rst(i_rst),
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.i_clk(i_clk),
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.o_clk(o_clk4)
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);
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// instantiate the clock divider with a divisor of 2
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clock_divider #(.DIVISOR(2)) cd2 (
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.i_rst(i_rst),
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.i_clk(i_clk),
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.o_clk(o_clk2)
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);
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// instantiate the clock divider with a divisor of 1
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clock_divider #(.DIVISOR(1)) cd1 (
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.i_rst(i_rst),
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.i_clk(i_clk),
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.o_clk(o_clk1)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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// generate a test sequence
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initial begin
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i_rst = 1; // reset the dividers
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#10;
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i_rst = 0; // release reset
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#300; // allow the simulation to run for some time
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$finish;
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end
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initial begin
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$dumpfile("build/clock_divider_tb.vcd");
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$dumpvars(0, clock_divider_tb);
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end
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endmodule
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