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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
79 lines
1.2 KiB
Systemverilog
79 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/demux8.v
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module demux8_tb;
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reg [2:0] i_sel;
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reg i_in;
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reg i_en;
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wire o_out0;
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wire o_out1;
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wire o_out2;
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wire o_out3;
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wire o_out4;
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wire o_out5;
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wire o_out6;
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wire o_out7;
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demux8 uut(
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.i_sel(i_sel),
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.i_in(i_in),
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.i_en(i_en),
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.o_out0(o_out0),
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.o_out1(o_out1),
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.o_out2(o_out2),
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.o_out3(o_out3),
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.o_out4(o_out4),
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.o_out5(o_out5),
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.o_out6(o_out6),
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.o_out7(o_out7)
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);
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// generate a clock
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initial begin
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i_in = 0;
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forever #5 i_in = ~i_in; // 10ns clock period, 100MHz
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end
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// generate a test sequence
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initial begin
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i_en = 1;
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i_sel = 3'b000;
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#30
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i_sel = 3'b001;
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#30
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i_sel = 3'b010;
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#30
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i_sel = 3'b011;
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#30
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i_sel = 3'b100;
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#30
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i_sel = 3'b101;
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#30
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i_sel = 3'b110;
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#30
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i_sel = 3'b111;
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#30
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i_en = 0;
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i_sel = 3'b000;
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#30
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i_sel = 3'b001;
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#30
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i_sel = 3'b010;
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#30
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#30
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$finish;
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end
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initial begin
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$dumpfile("build/demux8_tb.vcd");
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$dumpvars(0, demux8_tb);
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end
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endmodule
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