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37 lines
696 B
Systemverilog
37 lines
696 B
Systemverilog
`timescale 1ns/1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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module example_tb;
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reg clk, rst;
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reg [7:0] data_in;
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wire [7:0] data_out;
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// Generate clock
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always #5 clk = ~clk;
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initial begin
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// Initialize signals
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clk = 0;
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rst = 1;
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data_in = 8'h00;
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// Reset pulse
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#10 rst = 0;
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// Test stimulus
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#20 data_in = 8'hA5;
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#20 data_in = 8'h5A;
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// Finish simulation
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#100 $finish;
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end
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initial begin
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$dumpfile("build/example_tb.vcd"); // Save waveforms
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$dumpvars(0, example_tb);
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end
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endmodule
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