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61 lines
1004 B
Systemverilog

`timescale 1ns/1ps
// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
// SPDX-License-Identifier: GPL-3.0-or-later
//TB_DEPS: src/mavg.v
module mavg_tb;
reg i_clk;
reg i_rst;
reg i_trig;
reg signed [15:0] i_sample;
wire signed [15:0] o_avg;
mavg #(.WIDTH(16), .DEPTH(16)) mavg (
.clk(i_clk),
.rst(i_rst),
.trig(i_trig),
.in_sample(i_sample),
.out_avg(o_avg)
);
// generate a clock
initial begin
i_clk = 0;
forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
end
initial begin
i_rst = 1;
i_sample = 0;
#10;
i_rst = 0;
#10;
for (int i = 0; i < 16; i = i + 1) begin
i_sample = $random;
i_trig = 1;
#30;
i_trig = 0;
#10;
end
for (int i = 0; i < 20; i = i + 1) begin
i_sample = 8;
i_trig = 1;
#10;
i_trig = 0;
#10;
end
$finish;
end
initial begin
$dumpfile("build/mavg_tb.vcd");
$dumpvars(0, mavg_tb);
end
endmodule