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61 lines
1004 B
Systemverilog
61 lines
1004 B
Systemverilog
`timescale 1ns/1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/mavg.v
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module mavg_tb;
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reg i_clk;
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reg i_rst;
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reg i_trig;
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reg signed [15:0] i_sample;
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wire signed [15:0] o_avg;
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mavg #(.WIDTH(16), .DEPTH(16)) mavg (
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.clk(i_clk),
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.rst(i_rst),
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.trig(i_trig),
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.in_sample(i_sample),
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.out_avg(o_avg)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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initial begin
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i_rst = 1;
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i_sample = 0;
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#10;
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i_rst = 0;
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#10;
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for (int i = 0; i < 16; i = i + 1) begin
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i_sample = $random;
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i_trig = 1;
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#30;
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i_trig = 0;
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#10;
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end
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for (int i = 0; i < 20; i = i + 1) begin
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i_sample = 8;
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i_trig = 1;
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#10;
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i_trig = 0;
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#10;
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end
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$finish;
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end
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initial begin
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$dumpfile("build/mavg_tb.vcd");
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$dumpvars(0, mavg_tb);
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end
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endmodule
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