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65 lines
1004 B
Systemverilog
65 lines
1004 B
Systemverilog
`timescale 1ns/1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/multiplier.v
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module multiplier_tb;
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reg i_clk;
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reg i_rst;
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reg i_start;
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reg signed [15:0] i_a;
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reg signed [15:0] i_b;
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wire signed [31:0] o_result;
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wire o_ready;
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multiplier16 multiplier (
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.clk(i_clk),
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.rst(i_rst),
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.start(i_start),
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.a(i_a),
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.b(i_b),
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.result(o_result),
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.ready(o_ready)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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initial begin
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i_rst = 1;
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i_start = 0;
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i_a = 0;
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i_b = 0;
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#10;
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i_rst = 0;
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#10;
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i_start = 1;
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i_a = 25;
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i_b = -18;
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#10;
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i_start = 0;
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#200;
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i_start = 1;
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i_a = -138;
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i_b = 254;
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#10;
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i_start = 0;
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#200;
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$finish;
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end
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initial begin
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$dumpfile("build/multiplier_tb.vcd");
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$dumpvars(0, multiplier_tb);
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end
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endmodule
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