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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
73 lines
1.2 KiB
Systemverilog
73 lines
1.2 KiB
Systemverilog
`timescale 1ns / 1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/number_blinker.v
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module number_blinker_tb;
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localparam PERIOD = 2;
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reg [7:0] i_number;
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reg i_clk;
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reg i_rst;
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reg i_trigger;
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wire o_signal;
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number_blinker #(
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.PERIOD(PERIOD),
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.GAP_PERIOD(15)
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) nb (
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.i_number(i_number),
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.i_clk(i_clk),
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.i_rst(i_rst),
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.i_trigger(i_trigger),
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.o_signal(o_signal)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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// generate a test sequence
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initial begin
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i_rst = 1; // reset the number blinker
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i_number = 8'd3;
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#10;
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i_rst = 0; // release reset
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i_trigger = 1;
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#10
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i_trigger = 0;
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#2000; // allow the simulation to run for some time
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i_number = 8'd0;
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i_trigger = 1;
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#10
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i_trigger = 0;
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#2000;
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i_number = 8'd1;
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#2000;
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i_number = 8'd10;
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i_trigger = 1;
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#10
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i_trigger = 0;
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#2000;
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$finish;
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end
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initial begin
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$dumpfile("build/number_blinker_tb.vcd");
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$dumpvars(0, number_blinker_tb);
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end
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endmodule
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