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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
56 lines
1.0 KiB
Systemverilog
56 lines
1.0 KiB
Systemverilog
`timescale 1ns / 1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/shift_register.v
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module shift_register_tb;
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localparam WIDTH = 8;
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localparam SHIFT_LEFT = 1;
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reg i_clk;
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reg i_rst;
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reg i_input;
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wire [WIDTH-1:0] o_data;
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shift_register #(.WIDTH(WIDTH), .SHIFT_LEFT(SHIFT_LEFT)) sr (
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.i_clk(i_clk),
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.i_rst(i_rst),
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.i_input(i_input),
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.o_data(o_data)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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// generate a test sequence
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initial begin
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i_rst = 1; // reset the shift register
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i_input = 0;
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#10;
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i_rst = 0; // release reset
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#10 i_input = 1;
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#10 i_input = 1;
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#10 i_input = 1;
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#10 i_input = 0;
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#10 i_input = 0;
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#10 i_input = 1;
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#100;
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i_input = 0;
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#100;
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$finish;
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end
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initial begin
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$dumpfile("build/shift_register_tb.vcd");
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$dumpvars(0, shift_register_tb);
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end
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endmodule
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