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https://gitlab.com/hyperglitch/jellyfish.git
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b4a27f8ac4
- testbenches updated with TB_DEPS directive for granular dependency definition - async_fifo added for transferring ADC data to QSPI - qspi reads fixed - adc_ctrl properly sampling the ADC - DAC tested and working - periodic ADC trigger added
53 lines
868 B
Systemverilog
53 lines
868 B
Systemverilog
`timescale 1ns / 1ps
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// SPDX-FileCopyrightText: 2025 Igor Brkic <igor@hyperglitch.com>
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// SPDX-License-Identifier: GPL-3.0-or-later
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//TB_DEPS: src/spi_dac.v
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module spi_dac_tb;
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reg [15:0] i_data;
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reg i_trigger;
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reg i_clk;
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wire ncs;
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wire sdi;
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wire sck;
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spi_dac nb (
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.i_data(i_data),
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.i_clk(i_clk),
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.i_trigger(i_trigger),
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.ncs(ncs),
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.sdi(sdi),
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.sck(sck)
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);
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// generate a clock
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initial begin
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i_clk = 0;
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forever #5 i_clk = ~i_clk; // 10ns clock period, 100MHz
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end
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// generate a test sequence
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initial begin
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i_data = 16'hAD51;
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i_trigger = 0;
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#10 i_trigger = 1;
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#10 i_trigger = 0;
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#1000;
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i_data = 16'h8023;
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#10 i_trigger = 1;
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#10 i_trigger = 0;
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#1000;
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$finish;
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end
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initial begin
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$dumpfile("build/spi_dac_tb.vcd");
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$dumpvars(0, spi_dac_tb);
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end
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endmodule
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