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Prefix TRACK, ARC and VIA.

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This commit is contained in:
Jeff Young 2021-06-11 22:07:02 +01:00
parent 63c263090f
commit 096e342386
123 changed files with 746 additions and 756 deletions
3d-viewer
3d_canvas
board_adapter.hcreate_3Dgraphic_brd_items.cppcreate_layer_items.cppeda_3d_canvas.cpp
3d_rendering
3d_render_raytracing
create_scene.cpprender_3d_raytrace.h
legacy
create_scene.cpp
common
CMakeLists.txt
gerbview
export_to_pcbnew.h
include
core
typeinfo.h
pcb_base_frame.h
pcbnew
autorouter
ar_autoplacer.cppar_matrix.h
board.cppboard.hboard_connected_item.hboard_design_settings.cppboard_items_to_polygon_shape_transform.cppcollectors.cpp
connectivity
connectivity_algo.cppconnectivity_data.cppconnectivity_data.hconnectivity_items.cppconnectivity_items.hfrom_to_cache.cpp
cross-probing.cpp
dialogs
dialog_board_statistics.cppdialog_board_statistics.hdialog_gendrill.cppdialog_global_deletion.cppdialog_global_edit_tracks_and_vias.cppdialog_net_inspector.cppdialog_net_inspector.hdialog_swap_layers.cppdialog_track_via_properties.cppdialog_unused_pad_layers.cpppanel_pcbnew_color_settings.cpp
drc
drc_engine.cppdrc_rtree.hdrc_test_provider.cppdrc_test_provider_annulus.cppdrc_test_provider_connectivity.cppdrc_test_provider_copper_clearance.cppdrc_test_provider_diff_pair_coupling.cppdrc_test_provider_hole_size.cppdrc_test_provider_hole_to_hole.cppdrc_test_provider_matched_length.cppdrc_test_provider_track_width.cppdrc_test_provider_via_diameter.cpp
edit.cppedit_track_width.cpp
exporters
export_d356.cppexport_gencad.cppexport_hyperlynx.cppexport_vrml.cppexporter_vrml.hgendrill_file_writer_base.cppgendrill_gerber_writer.cppgerber_jobfile_writer.cpp
footprint.cppkicad_clipboard.cppnetinfo_item.cppnetinfo_list.cpp
netlist_reader
board_netlist_updater.cpp
pad.hpcb_base_frame.cpppcb_draw_panel_gal.cpppcb_edit_frame.cpppcb_edit_frame.hpcb_expr_evaluator.cpppcb_item_containers.hpcb_painter.cpppcb_painter.hpcb_track.cpppcb_track.hpcbnew_printout.cpppcbnew_printout.hplot_board_layers.cppplot_brditems_plotter.cpp
plugins
altium
altium_pcb.cpp
cadstar
cadstar_pcb_archive_loader.cppcadstar_pcb_archive_loader.h
eagle
eagle_plugin.cpp
fabmaster
import_fabmaster.cpp
kicad
kicad_plugin.cppkicad_plugin.hpcb_parser.cpppcb_parser.h
legacy
legacy_plugin.cpplegacy_plugin.h
pcad
pcb_line.cpppcb_pad.cpp
python
scripting
pcbnew_action_plugins.cpp
swig
board_item.itrack.i
ratsnest
ratsnest.cpp
router
pns_kicad_iface.cpppns_kicad_iface.hpns_sizes_settings.hpns_via.hrouter_tool.cpprouter_tool.h
specctra_import_export
specctra.cppspecctra.hspecctra_export.cppspecctra_import.cpp
tools
board_editor_control.cppconvert_tool.cppdrawing_tool.cppdrc_tool.hedit_tool.cppglobal_edit_tool.cpppcb_control.cpppcb_grid_helper.cpppcb_selection.cpppcb_selection_tool.cpp
tracks_cleaner.cpptracks_cleaner.hundo_redo.cppzone_filler.cpp
qa
libeval_compiler
libeval_compiler_test.cpp
pcbnew
test_libeval_compiler.cpp
pcbnew_tools/tools/polygon_generator
polygon_generator.cpp

5
3d-viewer/3d_canvas/board_adapter.h
View File

@ -37,7 +37,7 @@
#include <layers_id_colors_and_visibility.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <wx/gdicmn.h>
#include <pcb_base_frame.h>
#include <pcb_text.h>
@ -564,7 +564,8 @@ private:
void destroyLayers();
// Helper functions to create the board
void createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer, int aClearanceValue );
void createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
int aClearanceValue );
void createPadWithClearance( const PAD *aPad, CONTAINER_2D_BASE* aDstContainer,
PCB_LAYER_ID aLayer, wxSize aClearanceValue ) const;

4
3d-viewer/3d_canvas/create_3Dgraphic_brd_items.cpp
View File

@ -226,7 +226,7 @@ void BOARD_ADAPTER::addFootprintShapesWithClearance( const FOOTPRINT* aFootprint
}
void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
void BOARD_ADAPTER::createTrack( const PCB_TRACK* aTrack, CONTAINER_2D_BASE* aDstContainer,
int aClearanceValue )
{
SFVEC2F start3DU( aTrack->GetStart().x * m_biuTo3Dunits,
@ -243,7 +243,7 @@ void BOARD_ADAPTER::createTrack( const TRACK* aTrack, CONTAINER_2D_BASE* aDstCon
case PCB_ARC_T:
{
const ARC* arc = static_cast<const ARC*>( aTrack );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( aTrack );
VECTOR2D center( arc->GetCenter() );
double arc_angle = arc->GetAngle();
double radius = arc->GetRadius();

40
3d-viewer/3d_canvas/create_layer_items.cpp
View File

@ -149,22 +149,22 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
m_averageHoleDiameter = 0;
// Prepare track list, convert in a vector. Calc statistic for the holes
std::vector< const TRACK *> trackList;
std::vector<const PCB_TRACK*> trackList;
trackList.clear();
trackList.reserve( m_board->Tracks().size() );
for( TRACK* track : m_board->Tracks() )
for( PCB_TRACK* track : m_board->Tracks() )
{
if( !Is3dLayerEnabled( track->GetLayer() ) ) // Skip non enabled layers
continue;
// Note: a TRACK holds normal segment tracks and
// also vias circles (that have also drill values)
// Note: a PCB_TRACK holds normal segment tracks and also vias circles (that have also
// drill values)
trackList.push_back( track );
if( track->Type() == PCB_VIA_T )
{
const VIA *via = static_cast< const VIA*>( track );
const PCB_VIA *via = static_cast< const PCB_VIA*>( track );
m_viaCount++;
m_averageViaHoleDiameter += via->GetDrillValue() * m_biuTo3Dunits;
}
@ -235,14 +235,14 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
// NOTE: Vias can be on multiple layers
if( !track->IsOnLayer( curr_layer_id ) )
continue;
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
const PCB_VIA *via = dyn_cast< const PCB_VIA*>( track );
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;
@ -260,7 +260,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
@ -268,14 +268,14 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// ADD VIAS and THT
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const VIATYPE viatype = via->GetViaType();
const float holediameter = via->GetDrillValue() * BiuTo3dUnits();
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const VIATYPE viatype = via->GetViaType();
const float holediameter = via->GetDrillValue() * BiuTo3dUnits();
// holes and layer copper extend half info cylinder wall to hide transition
const float thickness = GetHolePlatingThickness() * BiuTo3dUnits() / 2.0f;
const float hole_inner_radius = ( holediameter / 2.0f );
const float ring_radius = via->GetWidth() * BiuTo3dUnits() / 2.0f;
const float thickness = GetHolePlatingThickness() * BiuTo3dUnits() / 2.0f;
const float hole_inner_radius = holediameter / 2.0f;
const float ring_radius = via->GetWidth() * BiuTo3dUnits() / 2.0f;
const SFVEC2F via_center( via->GetStart().x * m_biuTo3Dunits,
-via->GetStart().y * m_biuTo3Dunits );
@ -337,7 +337,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
@ -345,12 +345,12 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
// ADD VIAS and THT
if( track->Type() == PCB_VIA_T )
{
const VIA *via = static_cast< const VIA*>( track );
const VIATYPE viatype = via->GetViaType();
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const VIATYPE viatype = via->GetViaType();
if( viatype != VIATYPE::THROUGH )
{
// Add VIA hole contours
// Add PCB_VIA hole contours
// Add outer holes of VIAs
SHAPE_POLY_SET *layerOuterHolesPoly = nullptr;
@ -430,13 +430,13 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
for( unsigned int trackIdx = 0; trackIdx < nTracks; ++trackIdx )
{
const TRACK *track = trackList[trackIdx];
const PCB_TRACK *track = trackList[trackIdx];
if( !track->IsOnLayer( curr_layer_id ) )
continue;
// Skip vias annulus when not connected on this layer (if removing is enabled)
const VIA *via = dyn_cast< const VIA*>( track );
const PCB_VIA *via = dyn_cast<const PCB_VIA*>( track );
if( via && !via->FlashLayer( curr_layer_id ) && IsCopperLayer( curr_layer_id ) )
continue;

2
3d-viewer/3d_canvas/eda_3d_canvas.cpp
View File

@ -742,7 +742,7 @@ void EDA_3D_CANVAS::OnMouseMove( wxMouseEvent& event )
case PCB_VIA_T:
case PCB_ARC_T:
{
TRACK* track = dynamic_cast<TRACK*>( rollOverItem );
PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( rollOverItem );
if( track )
{

6
3d-viewer/3d_rendering/3d_render_raytracing/create_scene.cpp
View File

@ -1023,7 +1023,7 @@ void RENDER_3D_RAYTRACE::Reload( REPORTER* aStatusReporter, REPORTER* aWarningRe
}
void RENDER_3D_RAYTRACE::insertHole( const VIA* aVia )
void RENDER_3D_RAYTRACE::insertHole( const PCB_VIA* aVia )
{
PCB_LAYER_ID top_layer, bottom_layer;
int radiusBUI = ( aVia->GetDrillValue() / 2 );
@ -1254,11 +1254,11 @@ void RENDER_3D_RAYTRACE::addPadsAndVias()
// Insert plated vertical holes inside the board
// Insert vias holes (vertical cylinders)
for( TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
for( PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
{
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
insertHole( via );
}
}

2
3d-viewer/3d_rendering/3d_render_raytracing/render_3d_raytrace.h
View File

@ -114,7 +114,7 @@ private:
float aZMax, const MATERIAL* aMaterial, const SFVEC3F& aObjColor );
void addPadsAndVias();
void insertHole( const VIA* aVia );
void insertHole( const PCB_VIA* aVia );
void insertHole( const PAD* aPad );
void loadModels( CONTAINER_3D& aDstContainer, bool aSkipMaterialInformation );
void addModels( CONTAINER_3D& aDstContainer, const S3DMODEL* a3DModel,

4
3d-viewer/3d_rendering/legacy/create_scene.cpp
View File

@ -737,11 +737,11 @@ void RENDER_3D_LEGACY::generateViasAndPads()
// Insert plated vertical holes inside the board
// Insert vias holes (vertical cylinders)
for( const TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
for( const PCB_TRACK* track : m_boardAdapter.GetBoard()->Tracks() )
{
if( track->Type() == PCB_VIA_T )
{
const VIA* via = static_cast<const VIA*>( track );
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const float holediameter = via->GetDrillValue() * m_boardAdapter.BiuTo3dUnits();
const int nrSegments = m_boardAdapter.GetCircleSegmentCount( via->GetDrillValue() );

2
common/CMakeLists.txt
View File

@ -529,7 +529,7 @@ set( PCB_COMMON_SRCS
${CMAKE_SOURCE_DIR}/pcbnew/pcb_text.cpp
${CMAKE_SOURCE_DIR}/pcbnew/board_stackup_manager/board_stackup.cpp
${CMAKE_SOURCE_DIR}/pcbnew/fp_text.cpp
${CMAKE_SOURCE_DIR}/pcbnew/track.cpp
${CMAKE_SOURCE_DIR}/pcbnew/pcb_track.cpp
${CMAKE_SOURCE_DIR}/pcbnew/zone.cpp
${CMAKE_SOURCE_DIR}/pcbnew/collectors.cpp
${CMAKE_SOURCE_DIR}/pcbnew/connectivity/connectivity_algo.cpp

2
gerbview/export_to_pcbnew.h
View File

@ -138,7 +138,7 @@ private:
void export_segarc_copper_item( const GERBER_DRAW_ITEM* aGbrItem, LAYER_NUM aLayer );
/**
* Basic write function to write a a #TRACK item to the board file from a non flashed item.
* Basic write function to write a a #PCB_TRACK to the board file from a non flashed item.
*/
void writeCopperLineItem( const wxPoint& aStart, const wxPoint& aEnd,
int aWidth, LAYER_NUM aLayer );

8
include/core/typeinfo.h
View File

@ -92,10 +92,10 @@ enum KICAD_T
PCB_FP_TEXT_T, ///< class FP_TEXT, text in a footprint
PCB_FP_SHAPE_T, ///< class FP_SHAPE, a footprint edge
PCB_FP_ZONE_T, ///< class ZONE, managed by a footprint
PCB_TRACE_T, ///< class TRACK, a track segment (segment on a copper layer)
PCB_VIA_T, ///< class VIA, a via (like a track segment on a copper layer)
PCB_ARC_T, ///< class ARC, an arc track segment on a copper layer
PCB_MARKER_T, ///< class MARKER_PCB, a marker used to show something
PCB_TRACE_T, ///< class PCB_TRACK, a track segment (segment on a copper layer)
PCB_VIA_T, ///< class PCB_VIA, a via (like a track segment on a copper layer)
PCB_ARC_T, ///< class PCB_ARC, an arc track segment on a copper layer
PCB_MARKER_T, ///< class PCB_MARKER, a marker used to show something
PCB_DIMENSION_T, ///< class PCB_DIMENSION_BASE: abstract dimension meta-type
PCB_DIM_ALIGNED_T, ///< class PCB_DIM_ALIGNED, a linear dimension (graphic item)
PCB_DIM_LEADER_T, ///< class PCB_DIM_LEADER, a leader dimension (graphic item)

1
include/pcb_base_frame.h
View File

@ -51,7 +51,6 @@ class BOARD;
class BOARD_CONNECTED_ITEM;
class COLOR_SETTINGS;
class FOOTPRINT;
class TRACK;
class PAD;
class EDA_3D_VIEWER;
class GENERAL_COLLECTOR;

1
pcbnew/autorouter/ar_autoplacer.cpp
View File

@ -31,7 +31,6 @@
#include <widgets/msgpanel.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_shape.h>
#include <pad.h>
#include <board_commit.h>

1
pcbnew/autorouter/ar_matrix.h
View File

@ -33,7 +33,6 @@
#include <layers_id_colors_and_visibility.h>
class PCB_SHAPE;
class TRACK;
class PAD;
class FOOTPRINT;

38
pcbnew/board.cpp
View File

@ -34,7 +34,7 @@
#include <board_commit.h>
#include <board.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <pcb_marker.h>
#include <pcb_group.h>
@ -116,7 +116,7 @@ BOARD::~BOARD()
m_footprints.clear();
for( TRACK* t : m_tracks )
for( PCB_TRACK* t : m_tracks )
delete t;
m_tracks.clear();
@ -307,7 +307,7 @@ TRACKS BOARD::TracksInNet( int aNetCode )
INSPECTOR_FUNC inspector = [aNetCode, &ret]( EDA_ITEM* item, void* testData )
{
TRACK* t = static_cast<TRACK*>( item );
PCB_TRACK* t = static_cast<PCB_TRACK*>( item );
if( t->GetNetCode() == aNetCode )
ret.push_back( t );
@ -315,7 +315,7 @@ TRACKS BOARD::TracksInNet( int aNetCode )
return SEARCH_RESULT::CONTINUE;
};
// visit this BOARD's TRACKs and VIAs with above TRACK INSPECTOR which
// visit this BOARD's PCB_TRACKs and PCB_VIAs with above TRACK INSPECTOR which
// appends all in aNetCode to ret.
Visit( inspector, nullptr, GENERAL_COLLECTOR::Tracks );
@ -546,7 +546,7 @@ void BOARD::SetElementVisibility( GAL_LAYER_ID aLayer, bool isEnabled )
// because we have a tool to show/hide ratsnest relative to a pad or a footprint
// so the hide/show option is a per item selection
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
track->SetLocalRatsnestVisible( isEnabled );
for( FOOTPRINT* footprint : Footprints() )
@ -644,9 +644,9 @@ void BOARD::Add( BOARD_ITEM* aBoardItem, ADD_MODE aMode )
}
if( aMode == ADD_MODE::APPEND || aMode == ADD_MODE::BULK_APPEND )
m_tracks.push_back( static_cast<TRACK*>( aBoardItem ) );
m_tracks.push_back( static_cast<PCB_TRACK*>( aBoardItem ) );
else
m_tracks.push_front( static_cast<TRACK*>( aBoardItem ) );
m_tracks.push_front( static_cast<PCB_TRACK*>( aBoardItem ) );
break;
@ -732,7 +732,7 @@ void BOARD::Remove( BOARD_ITEM* aBoardItem, REMOVE_MODE aRemoveMode )
zone->SetNet( unconnected );
}
for( TRACK* track : m_tracks )
for( PCB_TRACK* track : m_tracks )
{
if( track->GetNet() == item )
track->SetNet( unconnected );
@ -869,7 +869,7 @@ BOARD_ITEM* BOARD::GetItem( const KIID& aID ) const
if( aID == niluuid )
return nullptr;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
{
if( track->m_Uuid == aID )
return track;
@ -948,7 +948,7 @@ void BOARD::FillItemMap( std::map<KIID, EDA_ITEM*>& aMap )
// the board itself
aMap[ m_Uuid ] = this;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
aMap[ track->m_Uuid ] = track;
for( FOOTPRINT* footprint : Footprints() )
@ -1144,7 +1144,7 @@ EDA_RECT BOARD::ComputeBoundingBox( bool aBoardEdgesOnly ) const
if( !aBoardEdgesOnly )
{
// Check tracks
for( TRACK* track : m_tracks )
for( PCB_TRACK* track : m_tracks )
{
if( ( track->GetLayerSet() & visible ).any() )
area.Merge( track->GetBoundingBox() );
@ -1168,7 +1168,7 @@ void BOARD::GetMsgPanelInfo( EDA_DRAW_FRAME* aFrame, std::vector<MSG_PANEL_ITEM>
int viasCount = 0;
int trackSegmentsCount = 0;
for( TRACK* item : m_tracks )
for( PCB_TRACK* item : m_tracks )
{
if( item->Type() == PCB_VIA_T )
viasCount++;
@ -1288,13 +1288,13 @@ SEARCH_RESULT BOARD::Visit( INSPECTOR inspector, void* testData, const KICAD_T s
break;
case PCB_VIA_T:
result = IterateForward<TRACK*>( m_tracks, inspector, testData, p );
result = IterateForward<PCB_TRACK*>( m_tracks, inspector, testData, p );
++p;
break;
case PCB_TRACE_T:
case PCB_ARC_T:
result = IterateForward<TRACK*>( m_tracks, inspector, testData, p );
result = IterateForward<PCB_TRACK*>( m_tracks, inspector, testData, p );
++p;
break;
@ -1572,7 +1572,7 @@ PAD* BOARD::GetPad( const wxPoint& aPosition, LSET aLayerSet ) const
}
PAD* BOARD::GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const
PAD* BOARD::GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const
{
const wxPoint& aPosition = aTrace->GetEndPoint( aEndPoint );
@ -1734,7 +1734,7 @@ void BOARD::PadDelete( PAD* aPad )
}
std::tuple<int, double, double> BOARD::GetTrackLength( const TRACK& aTrack ) const
std::tuple<int, double, double> BOARD::GetTrackLength( const PCB_TRACK& aTrack ) const
{
int count = 0;
double length = 0.0;
@ -1750,11 +1750,11 @@ std::tuple<int, double, double> BOARD::GetTrackLength( const TRACK& aTrack ) con
{
count++;
if( TRACK* track = dynamic_cast<TRACK*>( item ) )
if( PCB_TRACK* track = dynamic_cast<PCB_TRACK*>( item ) )
{
if( track->Type() == PCB_VIA_T && useHeight )
{
VIA* via = static_cast<VIA*>( track );
PCB_VIA* via = static_cast<PCB_VIA*>( track );
length += stackup.GetLayerDistance( via->TopLayer(), via->BottomLayer() );
continue;
}
@ -2018,7 +2018,7 @@ const std::vector<BOARD_CONNECTED_ITEM*> BOARD::AllConnectedItems()
{
std::vector<BOARD_CONNECTED_ITEM*> items;
for( TRACK* track : Tracks() )
for( PCB_TRACK* track : Tracks() )
items.push_back( track );
for( FOOTPRINT* footprint : Footprints() )

8
pcbnew/board.h
View File

@ -47,7 +47,7 @@ class PICKED_ITEMS_LIST;
class BOARD;
class FOOTPRINT;
class ZONE;
class TRACK;
class PCB_TRACK;
class PAD;
class PCB_GROUP;
class PCB_MARKER;
@ -927,11 +927,11 @@ public:
/**
* Find a pad connected to \a aEndPoint of \a aTrace.
*
* @param aTrace A pointer to a TRACK object to hit test against.
* @param aTrace A pointer to a PCB_TRACK object to hit test against.
* @param aEndPoint The end point of \a aTrace the hit test against.
* @return A pointer to a PAD object if found or NULL if not found.
*/
PAD* GetPad( const TRACK* aTrace, ENDPOINT_T aEndPoint ) const;
PAD* GetPad( const PCB_TRACK* aTrace, ENDPOINT_T aEndPoint ) const;
/**
* Return pad found at \a aPosition on \a aLayerMask using the fast search method.
@ -988,7 +988,7 @@ public:
* @param aTrack Starting track (can also be a via) to check against for connection.
* @return a tuple containing <number, length, package length>
*/
std::tuple<int, double, double> GetTrackLength( const TRACK& aTrack ) const;
std::tuple<int, double, double> GetTrackLength( const PCB_TRACK& aTrack ) const;
/**
* Collect all the TRACKs and VIAs that are members of a net given by aNetCode.

1
pcbnew/board_connected_item.h
View File

@ -30,7 +30,6 @@
class NETCLASS;
class NETINFO_ITEM;
class TRACK;
class PAD;
/**

2
pcbnew/board_design_settings.cpp
View File

@ -22,7 +22,7 @@
*/
#include <pcb_dimension.h>
#include <track.h>
#include <pcb_track.h>
#include <layers_id_colors_and_visibility.h>
#include <kiface_i.h>
#include <pad.h>

16
pcbnew/board_items_to_polygon_shape_transform.cpp
View File

@ -29,7 +29,7 @@
#include <board.h>
#include <pad.h>
#include <pcb_dimension.h>
#include <track.h>
#include <pcb_track.h>
#include <kicad_string.h>
#include <pcb_shape.h>
#include <pcb_text.h>
@ -72,7 +72,7 @@ void BOARD::ConvertBrdLayerToPolygonalContours( PCB_LAYER_ID aLayer, SHAPE_POLY_
int maxError = GetDesignSettings().m_MaxError;
// convert tracks and vias:
for( const TRACK* track : m_tracks )
for( const PCB_TRACK* track : m_tracks )
{
if( !track->IsOnLayer( aLayer ) )
continue;
@ -538,10 +538,10 @@ void PCB_SHAPE::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuf
}
void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
PCB_LAYER_ID aLayer, int aClearanceValue,
int aError, ERROR_LOC aErrorLoc,
bool ignoreLineWidth ) const
void PCB_TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
PCB_LAYER_ID aLayer, int aClearanceValue,
int aError, ERROR_LOC aErrorLoc,
bool ignoreLineWidth ) const
{
wxASSERT_MSG( !ignoreLineWidth, "IgnoreLineWidth has no meaning for tracks." );
@ -557,8 +557,8 @@ void TRACK::TransformShapeWithClearanceToPolygon( SHAPE_POLY_SET& aCornerBuffer,
case PCB_ARC_T:
{
const ARC* arc = static_cast<const ARC*>( this );
int width = m_Width + ( 2 * aClearanceValue );
const PCB_ARC* arc = static_cast<const PCB_ARC*>( this );
int width = m_Width + ( 2 * aClearanceValue );
TransformArcToPolygon( aCornerBuffer, arc->GetStart(), arc->GetMid(),
arc->GetEnd(), width, aError, aErrorLoc );

6
pcbnew/collectors.cpp
View File

@ -28,7 +28,7 @@
#include <footprint.h>
#include <fp_shape.h>
#include <pad.h>
#include <track.h>
#include <pcb_track.h>
#include <pcb_marker.h>
#include <pcb_dimension.h>
#include <zone.h>
@ -161,7 +161,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
PCB_GROUP* group = nullptr;
PAD* pad = nullptr;
bool pad_through = false;
VIA* via = nullptr;
PCB_VIA* via = nullptr;
PCB_MARKER* marker = nullptr;
ZONE* zone = nullptr;
PCB_SHAPE* shape = nullptr;
@ -258,7 +258,7 @@ SEARCH_RESULT GENERAL_COLLECTOR::Inspect( EDA_ITEM* testItem, void* testData )
break;
case PCB_VIA_T: // vias are on many layers, so layer test is specific
via = static_cast<VIA*>( item );
via = static_cast<PCB_VIA*>( item );
break;
case PCB_TRACE_T:

14
pcbnew/connectivity/connectivity_algo.cpp
View File

@ -148,21 +148,21 @@ bool CN_CONNECTIVITY_ALGO::Add( BOARD_ITEM* aItem )
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<TRACK*>( aItem ) );
add( m_itemList, static_cast<PCB_TRACK*>( aItem ) );
break;
case PCB_ARC_T:
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<ARC*>( aItem ) );
add( m_itemList, static_cast<PCB_ARC*>( aItem ) );
break;
case PCB_VIA_T:
if( m_itemMap.find( aItem ) != m_itemMap.end() )
return false;
add( m_itemList, static_cast<VIA*>( aItem ) );
add( m_itemList, static_cast<PCB_VIA*>( aItem ) );
break;
case PCB_ZONE_T:
@ -436,7 +436,7 @@ void CN_CONNECTIVITY_ALGO::Build( BOARD* aBoard, PROGRESS_REPORTER* aReporter )
reportProgress( aReporter, ii++, size, delta );
}
for( TRACK* tv : aBoard->Tracks() )
for( PCB_TRACK* tv : aBoard->Tracks() )
{
Add( tv );
reportProgress( aReporter, ii++, size, delta );
@ -657,7 +657,7 @@ void CN_VISITOR::checkZoneItemConnection( CN_ZONE_LAYER* aZoneLayer, CN_ITEM* aI
|| aItem->Parent()->Type() == PCB_TRACE_T
|| aItem->Parent()->Type() == PCB_ARC_T )
{
accuracy = ( static_cast<TRACK*>( aItem->Parent() )->GetWidth() + 1 ) / 2;
accuracy = ( static_cast<PCB_TRACK*>( aItem->Parent() )->GetWidth() + 1 ) / 2;
}
for( int i = 0; i < aItem->AnchorCount(); ++i )
@ -776,12 +776,12 @@ bool CN_VISITOR::operator()( CN_ITEM* aCandidate )
if( parentA->Type() == PCB_VIA_T
|| parentA->Type() == PCB_TRACE_T
|| parentA->Type() == PCB_ARC_T)
accuracyA = ( static_cast<const TRACK*>( parentA )->GetWidth() + 1 ) / 2;
accuracyA = ( static_cast<const PCB_TRACK*>( parentA )->GetWidth() + 1 ) / 2;
if( parentB->Type() == PCB_VIA_T
|| parentB->Type() == PCB_TRACE_T
|| parentB->Type() == PCB_ARC_T )
accuracyB = ( static_cast<const TRACK*>( parentB )->GetWidth() + 1 ) / 2;
accuracyB = ( static_cast<const PCB_TRACK*>( parentB )->GetWidth() + 1 ) / 2;
// Items do not necessarily have reciprocity as we only check for anchors
// therefore, we check HitTest both directions A->B & B->A

16
pcbnew/connectivity/connectivity_data.cpp
View File

@ -484,23 +484,23 @@ bool CONNECTIVITY_DATA::CheckConnectivity( std::vector<CN_DISJOINT_NET_ENTRY>& a
}
const std::vector<TRACK*> CONNECTIVITY_DATA::GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem )
const
const std::vector<PCB_TRACK*> CONNECTIVITY_DATA::GetConnectedTracks(
const BOARD_CONNECTED_ITEM* aItem ) const
{
auto& entry = m_connAlgo->ItemEntry( aItem );
std::set<TRACK*> tracks;
std::vector<TRACK*> rv;
std::set<PCB_TRACK*> tracks;
std::vector<PCB_TRACK*> rv;
for( auto citem : entry.GetItems() )
for( CN_ITEM* citem : entry.GetItems() )
{
for( auto connected : citem->ConnectedItems() )
for( CN_ITEM* connected : citem->ConnectedItems() )
{
if( connected->Valid() &&
( connected->Parent()->Type() == PCB_TRACE_T ||
connected->Parent()->Type() == PCB_VIA_T ||
connected->Parent()->Type() == PCB_ARC_T ) )
tracks.insert( static_cast<TRACK*> ( connected->Parent() ) );
tracks.insert( static_cast<PCB_TRACK*> ( connected->Parent() ) );
}
}
@ -586,7 +586,7 @@ void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges) const
}
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos )
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos )
{
auto items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();

9
pcbnew/connectivity/connectivity_data.h
View File

@ -50,7 +50,7 @@ class BOARD_ITEM;
class ZONE;
class RN_DATA;
class RN_NET;
class TRACK;
class PCB_TRACK;
class PAD;
class FOOTPRINT;
class PROGRESS_REPORTER;
@ -195,13 +195,14 @@ public:
*/
unsigned int GetUnconnectedCount() const;
bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem, int aLayer, std::vector<KICAD_T> aTypes = {} ) const;
bool IsConnectedOnLayer( const BOARD_CONNECTED_ITEM* aItem,
int aLayer, std::vector<KICAD_T> aTypes = {} ) const;
unsigned int GetNodeCount( int aNet = -1 ) const;
unsigned int GetPadCount( int aNet = -1 ) const;
const std::vector<TRACK*> GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const;
const std::vector<PCB_TRACK*> GetConnectedTracks( const BOARD_CONNECTED_ITEM* aItem ) const;
const std::vector<PAD*> GetConnectedPads( const BOARD_CONNECTED_ITEM* aItem ) const;
@ -225,7 +226,7 @@ public:
void GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges ) const;
bool TestTrackEndpointDangling( TRACK* aTrack, wxPoint* aPos = nullptr );
bool TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos = nullptr );
/**
* Function ClearDynamicRatsnest()

18
pcbnew/connectivity/connectivity_items.cpp
View File

@ -138,12 +138,12 @@ const VECTOR2I CN_ITEM::GetAnchor( int n ) const
case PCB_TRACE_T:
case PCB_ARC_T:
if( n == 0 )
return static_cast<const TRACK*>( m_parent )->GetStart();
return static_cast<const PCB_TRACK*>( m_parent )->GetStart();
else
return static_cast<const TRACK*>( m_parent )->GetEnd();
return static_cast<const PCB_TRACK*>( m_parent )->GetEnd();
case PCB_VIA_T:
return static_cast<const VIA*>( m_parent )->GetStart();
return static_cast<const PCB_VIA*>( m_parent )->GetStart();
default:
assert( false );
@ -158,9 +158,9 @@ void CN_ITEM::Dump()
{
wxLogDebug(" valid: %d, connected: \n", !!Valid());
for( auto i : m_connected )
for( CN_ITEM* i : m_connected )
{
TRACK* t = static_cast<TRACK*>( i->Parent() );
PCB_TRACK* t = static_cast<PCB_TRACK*>( i->Parent() );
wxLogDebug( " - %p %d\n", t, t->Type() );
}
}
@ -239,7 +239,7 @@ CN_ITEM* CN_LIST::Add( PAD* pad )
return item;
}
CN_ITEM* CN_LIST::Add( TRACK* track )
CN_ITEM* CN_LIST::Add( PCB_TRACK* track )
{
auto item = new CN_ITEM( track, true );
m_items.push_back( item );
@ -251,7 +251,7 @@ CN_ITEM* CN_LIST::Add( TRACK* track )
return item;
}
CN_ITEM* CN_LIST::Add( ARC* aArc )
CN_ITEM* CN_LIST::Add( PCB_ARC* aArc )
{
auto item = new CN_ITEM( aArc, true );
m_items.push_back( item );
@ -263,7 +263,7 @@ CN_ITEM* CN_LIST::Add( ARC* aArc )
return item;
}
CN_ITEM* CN_LIST::Add( VIA* via )
CN_ITEM* CN_LIST::Add( PCB_VIA* via )
{
auto item = new CN_ITEM( via, !via->GetIsFree(), 1 );
@ -365,7 +365,7 @@ bool CN_ANCHOR::IsDangling() const
return connected_count < minimal_count;
if( Parent()->Type() == PCB_TRACE_T || Parent()->Type() == PCB_ARC_T )
accuracy = ( static_cast<const TRACK*>( Parent() )->GetWidth() + 1 )/ 2;
accuracy = ( static_cast<const PCB_TRACK*>( Parent() )->GetWidth() + 1 ) / 2;
// Items with multiple anchors have usually items connected to each anchor.
// We want only the item count of this anchor point

8
pcbnew/connectivity/connectivity_items.h
View File

@ -32,7 +32,7 @@
#include <board.h>
#include <pad.h>
#include <footprint.h>
#include <track.h>
#include <pcb_track.h>
#include <zone.h>
#include <geometry/shape_poly_set.h>
@ -432,11 +432,11 @@ public:
CN_ITEM* Add( PAD* pad );
CN_ITEM* Add( TRACK* track );
CN_ITEM* Add( PCB_TRACK* track );
CN_ITEM* Add( ARC* track );
CN_ITEM* Add( PCB_ARC* track );
CN_ITEM* Add( VIA* via );
CN_ITEM* Add( PCB_VIA* via );
const std::vector<CN_ITEM*> Add( ZONE* zone, PCB_LAYER_ID aLayer );

1
pcbnew/connectivity/from_to_cache.cpp
View File

@ -21,7 +21,6 @@
#include <memory>
#include <reporter.h>
#include <board.h>
#include <track.h>
#include <kicad_string.h>
#include <pcb_expr_evaluator.h>

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