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Added DRC test for minimum/maximum segment length

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Checks segment lengths, optionally flagging segments that are minor-size and thus hard to see
This commit is contained in:
Daniel Treffenstädt 2024-10-18 19:48:08 +00:00 committed by Seth Hillbrand
parent 10d23ada48
commit 2200eebc06
11 changed files with 227 additions and 1 deletions

1
common/drc_rules.keywords
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@ -52,6 +52,7 @@ thermal_spoke_width
track
track_angle
track_width
track_segment_length
version
via
via_count

1
pcbnew/CMakeLists.txt
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@ -272,6 +272,7 @@ set( PCBNEW_DRC_SRCS
drc/drc_test_provider_text_dims.cpp
drc/drc_test_provider_track_angle.cpp
drc/drc_test_provider_track_width.cpp
drc/drc_test_provider_track_segment_length.cpp
drc/drc_test_provider_zone_connections.cpp
drc/drc_test_provider_via_diameter.cpp
drc/drc_test_provider_solder_mask.cpp

2
pcbnew/dialogs/panel_setup_rules.cpp
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@ -265,6 +265,7 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
|| token == wxT( "thermal_spoke_width" )
|| token == wxT( "track_width" )
|| token == wxT( "track_angle" )
|| token == wxT( "track_segment_length" )
|| token == wxT( "via_count" )
|| token == wxT( "via_diameter" )
|| token == wxT( "zone_connection" );
@ -482,6 +483,7 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
"thermal_spoke_width|"
"track_width|"
"track_angle|"
"track_segment_length|"
"via_count|"
"via_diameter|"
"zone_connection" );

1
pcbnew/dialogs/panel_setup_rules_help.md
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@ -44,6 +44,7 @@
| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> |
| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |
| `track_angle` | min/opt/max | Checks the angle between two connected track segments. An error will be generated for each connected pair with an angle below the `min` value (if specified) or above the `max` value (if specified).<br> |
| `track_segment_length` | min/max | Checks the length of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |
| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> |
| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` | Specifies the connection to be made between a zone and a pad.<br> |

1
pcbnew/dialogs/panel_setup_rules_help_md.h
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@ -45,6 +45,7 @@ _HKI( "### Top-level Clauses\n"
"| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> |\n"
"| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |\n"
"| `track_angle` | min/opt/max | Checks the angle between two connected track segments. An error will be generated for each connected pair with an angle below the `min` value (if specified) or above the `max` value (if specified).<br> |\n"
"| `track_segment_length` | min/max | Checks the length of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |\n"
"| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> |\n"
"| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` | Specifies the connection to be made between a zone and a pad.<br> |\n"
"\n"

6
pcbnew/drc/drc_item.cpp
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@ -126,6 +126,10 @@ DRC_ITEM DRC_ITEM::trackAngle( DRCE_TRACK_ANGLE,
_( "Track angle" ),
wxT( "track_angle" ) );
DRC_ITEM DRC_ITEM::trackSegmentLength( DRCE_TRACK_SEGMENT_LENGTH,
_( "Track segment length" ),
wxT( "track_segment_length" ) );
DRC_ITEM DRC_ITEM::annularWidth( DRCE_ANNULAR_WIDTH,
_( "Annular width" ),
wxT( "annular_width" ) );
@ -306,6 +310,7 @@ std::vector<std::reference_wrapper<RC_ITEM>> DRC_ITEM::allItemTypes(
DRC_ITEM::holesCoLocated,
DRC_ITEM::trackWidth,
DRC_ITEM::trackAngle,
DRC_ITEM::trackSegmentLength,
DRC_ITEM::annularWidth,
DRC_ITEM::drillTooSmall,
DRC_ITEM::microviaDrillTooSmall,
@ -387,6 +392,7 @@ std::shared_ptr<DRC_ITEM> DRC_ITEM::Create( int aErrorCode )
case DRCE_CONNECTION_WIDTH: return std::make_shared<DRC_ITEM>( connectionWidth );
case DRCE_TRACK_WIDTH: return std::make_shared<DRC_ITEM>( trackWidth );
case DRCE_TRACK_ANGLE: return std::make_shared<DRC_ITEM>( trackAngle );
case DRCE_TRACK_SEGMENT_LENGTH: return std::make_shared<DRC_ITEM>( trackSegmentLength );
case DRCE_ANNULAR_WIDTH: return std::make_shared<DRC_ITEM>( annularWidth );
case DRCE_DRILL_OUT_OF_RANGE: return std::make_shared<DRC_ITEM>( drillTooSmall );
case DRCE_VIA_DIAMETER: return std::make_shared<DRC_ITEM>( viaDiameter );

2
pcbnew/drc/drc_item.h
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@ -54,6 +54,7 @@ enum PCB_DRC_CODE {
DRCE_HOLE_CLEARANCE, //
DRCE_TRACK_WIDTH, // Track width is too small or too large
DRCE_TRACK_ANGLE, // Angle between two connected tracks is too small or too large
DRCE_TRACK_SEGMENT_LENGTH, // Track segment is too short or too long
DRCE_ANNULAR_WIDTH, // Via size and drill leave annular ring too small
DRCE_CONNECTION_WIDTH, // Net connection too small
DRCE_DRILL_OUT_OF_RANGE, // Too small via or pad drill
@ -194,6 +195,7 @@ private:
static DRC_ITEM connectionWidth;
static DRC_ITEM trackWidth;
static DRC_ITEM trackAngle;
static DRC_ITEM trackSegmentLength;
static DRC_ITEM annularWidth;
static DRC_ITEM drillTooSmall;
static DRC_ITEM viaDiameter;

1
pcbnew/drc/drc_rule.h
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@ -57,6 +57,7 @@ enum DRC_CONSTRAINT_T
TEXT_HEIGHT_CONSTRAINT,
TEXT_THICKNESS_CONSTRAINT,
TRACK_WIDTH_CONSTRAINT,
TRACK_SEGMENT_LENGTH_CONSTRAINT,
ANNULAR_WIDTH_CONSTRAINT,
ZONE_CONNECTION_CONSTRAINT,
THERMAL_RELIEF_GAP_CONSTRAINT,

3
pcbnew/drc/drc_rule_parser.cpp
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@ -317,6 +317,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
case T_text_thickness: c.m_Type = TEXT_THICKNESS_CONSTRAINT; break;
case T_track_width: c.m_Type = TRACK_WIDTH_CONSTRAINT; break;
case T_track_angle: c.m_Type = TRACK_ANGLE_CONSTRAINT; break;
case T_track_segment_length: c.m_Type = TRACK_SEGMENT_LENGTH_CONSTRAINT; break;
case T_connection_width: c.m_Type = CONNECTION_WIDTH_CONSTRAINT; break;
case T_annular_width: c.m_Type = ANNULAR_WIDTH_CONSTRAINT; break;
case T_via_diameter: c.m_Type = VIA_DIAMETER_CONSTRAINT; break;
@ -336,7 +337,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
msg.Printf( _( "Unrecognized item '%s'.| Expected %s." ), FromUTF8(),
wxT( "assertion, clearance, hole_clearance, edge_clearance, "
"physical_clearance, physical_hole_clearance, courtyard_clearance, "
"silk_clearance, hole_size, hole_to_hole, track_width, track_angle, annular_width, "
"silk_clearance, hole_size, hole_to_hole, track_width, track_angle, track_segment_length, annular_width, "
"disallow, zone_connection, thermal_relief_gap, thermal_spoke_width, "
"min_resolved_spokes, length, skew, via_count, via_diameter, "
"diff_pair_gap or diff_pair_uncoupled" ) );

194
pcbnew/drc/drc_test_provider_track_segment_length.cpp Normal file
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@ -0,0 +1,194 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004-2023 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <core/thread_pool.h>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider.h>
/*
Track segment length test. As the name says, checks segment length of the tracks (including segments and arcs)
Errors generated:
- DRCE_TRACK_SEGMENT_LENGTH
*/
class DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH : public DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH()
{}
virtual ~DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH()
{}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "segment_length" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Tests track segment lengths" );
}
};
bool DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH::Run()
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TRACK_SEGMENT_LENGTH ) )
{
reportAux( wxT( "Track segment length violations ignored. Tests not run." ) );
return true; // continue with other tests
}
if( !m_drcEngine->HasRulesForConstraintType( TRACK_SEGMENT_LENGTH_CONSTRAINT ) )
{
reportAux( wxT( "No track segment length constraints found. Tests not run." ) );
return true; // continue with other tests
}
if( !reportPhase( _( "Checking track segment lengths..." ) ) )
return false; // DRC cancelled
auto checkTrackSegmentLength =
[&]( BOARD_ITEM* item ) -> bool
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TRACK_SEGMENT_LENGTH ) )
return false;
int actual;
VECTOR2I p0;
if( item->Type() == PCB_ARC_T )
{
PCB_ARC* arc = static_cast<PCB_ARC*>( item );
actual = arc->GetLength();
p0 = arc->GetStart();
}
else if( item->Type() == PCB_TRACE_T )
{
PCB_TRACK* track = static_cast<PCB_TRACK*>( item );
actual = track->GetLength();
p0 = ( track->GetStart() + track->GetEnd() ) / 2;
}
else
{
return true;
}
auto constraint = m_drcEngine->EvalRules( TRACK_SEGMENT_LENGTH_CONSTRAINT, item, nullptr,
item->GetLayer() );
bool fail_min = false;
bool fail_max = false;
int constraintLength = 0;
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
if( constraint.Value().HasMin() && actual < constraint.Value().Min() )
{
fail_min = true;
constraintLength = constraint.Value().Min();
}
if( constraint.Value().HasMax() && actual > constraint.Value().Max() )
{
fail_max = true;
constraintLength = constraint.Value().Max();
}
}
if( fail_min || fail_max )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACK_SEGMENT_LENGTH );
wxString constraintName = constraint.GetName();
wxString msg;
if( fail_min )
{
if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
constraintName = _( "board setup constraints" );
msg = formatMsg( _( "(%s min length %s; actual %s)" ),
constraintName,
constraintLength,
actual );
}
else
{
msg = formatMsg( _( "(%s max length %s; actual %s)" ),
constraintName,
constraintLength,
actual );
}
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, p0, item->GetLayer() );
}
return true;
};
const int progressDelta = 250;
int ii = 0;
thread_pool& tp = GetKiCadThreadPool();
std::vector<std::future<bool>> returns;
returns.reserve( m_drcEngine->GetBoard()->Tracks().size() );
for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() )
{
returns.emplace_back( tp.submit( checkTrackSegmentLength, item ) );
}
for( std::future<bool>& ret : returns )
{
std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
while( status != std::future_status::ready )
{
reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), progressDelta );
status = ret.wait_for( std::chrono::milliseconds( 250 ) );
}
}
reportRuleStatistics();
return !m_drcEngine->IsCancelled();
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH> dummy;
}

16
pcbnew/tools/board_inspection_tool.cpp
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@ -310,6 +310,7 @@ wxString BOARD_INSPECTION_TOOL::InspectDRCErrorMenuText( const std::shared_ptr<R
|| aDRCItem->GetErrorCode() == DRCE_DIFF_PAIR_UNCOUPLED_LENGTH_TOO_LONG
|| aDRCItem->GetErrorCode() == DRCE_TRACK_WIDTH
|| aDRCItem->GetErrorCode() == DRCE_TRACK_ANGLE
|| aDRCItem->GetErrorCode() == DRCE_TRACK_SEGMENT_LENGTH
|| aDRCItem->GetErrorCode() == DRCE_VIA_DIAMETER
|| aDRCItem->GetErrorCode() == DRCE_ANNULAR_WIDTH
|| aDRCItem->GetErrorCode() == DRCE_DRILL_OUT_OF_RANGE
@ -457,6 +458,21 @@ void BOARD_INSPECTION_TOOL::InspectDRCError( const std::shared_ptr<RC_ITEM>& aDR
reportMax( m_frame, constraint ) ) );
break;
case DRCE_TRACK_SEGMENT_LENGTH:
r = dialog->AddHTMLPage( _( "Track Segment Length" ) );
reportHeader( _( "Track segment length resolution for:" ), a, r );
if( compileError )
reportCompileError( r );
constraint = drcEngine->EvalRules( TRACK_SEGMENT_LENGTH_CONSTRAINT, a, b, layer, r );
r->Report( "" );
r->Report( wxString::Format( _( "Resolved segment length constraints: min %s; max %s." ),
reportMin( m_frame, constraint ),
reportMax( m_frame, constraint ) ) );
break;
case DRCE_CONNECTION_WIDTH:
r = dialog->AddHTMLPage( _( "Connection Width" ) );
reportHeader( _( "Connection width resolution for:" ), a, b, r );