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Infrastructure and file format for via stacks

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This commit is contained in:
Jon Evans 2024-10-06 16:34:15 -04:00
parent fac5f6aa83
commit 2a605e4a4e
38 changed files with 355 additions and 114 deletions

4
3d-viewer/3d_canvas/create_layer_items.cpp
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@ -303,7 +303,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
const PCB_VIA* via = static_cast<const PCB_VIA*>( track );
const VIATYPE viatype = via->GetViaType();
const double holediameter = via->GetDrillValue() * BiuTo3dUnits();
const double viasize = via->GetWidth() * BiuTo3dUnits();
const double viasize = via->GetWidth( layer ) * BiuTo3dUnits();
const double plating = GetHolePlatingThickness() * BiuTo3dUnits();
// holes and layer copper extend half info cylinder wall to hide transition
@ -428,7 +428,7 @@ void BOARD_ADAPTER::createLayers( REPORTER* aStatusReporter )
{
const int holediameter = via->GetDrillValue();
const int hole_outer_radius = (holediameter / 2) + GetHolePlatingThickness();
const int hole_outer_ring_radius = KiROUND( via->GetWidth() / 2.0 );
const int hole_outer_ring_radius = KiROUND( via->GetWidth( layer ) / 2.0 );
// Add through hole contours
TransformCircleToPolygon( m_TH_ODPolys, via->GetStart(), hole_outer_radius,

5
common/hash_eda.cpp
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@ -80,14 +80,15 @@ size_t hash_fp_item( const EDA_ITEM* aItem, int aFlags )
case PCB_VIA_T:
{
const PCB_VIA* via = static_cast<const PCB_VIA*>( aItem );
ret = hash_val( via->GetWidth() );
hash_combine( ret, via->GetDrillValue() );
ret = hash<int>{}( via->GetDrillValue() );
hash_combine( ret, via->TopLayer() );
hash_combine( ret, via->BottomLayer() );
via->GetLayerSet().RunOnLayers(
[&]( PCB_LAYER_ID layer )
{
hash_combine( ret, via->GetWidth( layer ) );
hash_combine( ret, via->FlashLayer( layer ) );
} );

5
pcbnew/connectivity/connectivity_data.cpp
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@ -485,8 +485,9 @@ bool CONNECTIVITY_DATA::IsConnectedOnLayer( const BOARD_CONNECTED_ITEM *aItem, i
if( zone->IsFilled() )
{
const SHAPE_POLY_SET* zoneFill = zone->GetFill( ToLAYER_ID( aLayer ) );
SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth() / 2 );
PCB_LAYER_ID lyr = ToLAYER_ID( aLayer );
const SHAPE_POLY_SET* zoneFill = zone->GetFill( lyr );
SHAPE_CIRCLE viaHull( via->GetCenter(), via->GetWidth( lyr ) / 2 );
for( const VECTOR2I& pt : zoneFill->COutline( islandIdx ).CPoints() )
{

7
pcbnew/dialogs/dialog_track_via_properties.cpp
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@ -212,7 +212,8 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen
{
m_viaX.SetValue( v->GetPosition().x );
m_viaY.SetValue( v->GetPosition().y );
m_viaDiameter.SetValue( v->GetWidth() );
// TODO(JE) padstacks
m_viaDiameter.SetValue( v->GetWidth( PADSTACK::ALL_LAYERS ) );
m_viaDrill.SetValue( v->GetDrillValue() );
m_vias = true;
viaType = v->GetViaType();
@ -249,7 +250,7 @@ DIALOG_TRACK_VIA_PROPERTIES::DIALOG_TRACK_VIA_PROPERTIES( PCB_BASE_FRAME* aParen
if( m_viaY.GetValue() != v->GetPosition().y )
m_viaY.SetValue( INDETERMINATE_STATE );
if( m_viaDiameter.GetValue() != v->GetWidth() )
if( m_viaDiameter.GetValue() != v->GetWidth( PADSTACK::ALL_LAYERS ) )
m_viaDiameter.SetValue( INDETERMINATE_STATE );
if( m_viaDrill.GetValue() != v->GetDrillValue() )
@ -709,7 +710,7 @@ bool DIALOG_TRACK_VIA_PROPERTIES::TransferDataFromWindow()
v->SanitizeLayers();
if( !m_viaDiameter.IsIndeterminate() )
v->SetWidth( m_viaDiameter.GetIntValue() );
v->SetWidth( PADSTACK::ALL_LAYERS, m_viaDiameter.GetIntValue() );
if( !m_viaDrill.IsIndeterminate() )
v->SetDrill( m_viaDrill.GetIntValue() );

3
pcbnew/drc/drc_test_provider_annular_width.cpp
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@ -259,7 +259,8 @@ bool DRC_TEST_PROVIDER_ANNULAR_WIDTH::Run()
case PCB_VIA_T:
{
PCB_VIA* via = static_cast<PCB_VIA*>( item );
annularWidth = ( via->GetWidth() - via->GetDrillValue() ) / 2;
// TODO(JE) padstacks
annularWidth = ( via->GetWidth( PADSTACK::ALL_LAYERS ) - via->GetDrillValue() ) / 2;
break;
}

3
pcbnew/drc/drc_test_provider_via_diameter.cpp
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@ -91,7 +91,8 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
bool fail_min = false;
bool fail_max = false;
int constraintDiameter = 0;
int actual = via->GetWidth();
// TODO(JE) padstacks
int actual = via->GetWidth( PADSTACK::ALL_LAYERS );
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{

3
pcbnew/exporters/export_d356.cpp
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@ -204,7 +204,8 @@ static void build_via_testpoints( BOARD *aPcb, std::vector <D356_RECORD>& aRecor
rk.access = via_access_code( aPcb, top_layer, bottom_layer );
rk.x_location = via->GetPosition().x - origin.x;
rk.y_location = origin.y - via->GetPosition().y;
rk.x_size = via->GetWidth();
// TODO(JE) padstacks
rk.x_size = via->GetWidth( PADSTACK::ALL_LAYERS );
rk.y_size = 0; // Round so height = 0
rk.rotation = 0;
rk.soldermask = 3; // XXX always tented?

14
pcbnew/exporters/export_gencad_writer.cpp
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@ -233,8 +233,8 @@ bool GENCAD_EXPORTER::WriteFile( const wxString& aFullFileName )
// Sort vias for uniqueness
static bool ViaSort( const PCB_VIA* aPadref, const PCB_VIA* aPadcmp )
{
if( aPadref->GetWidth() != aPadcmp->GetWidth() )
return aPadref->GetWidth() < aPadcmp->GetWidth();
if( aPadref->GetWidth( PADSTACK::ALL_LAYERS ) != aPadcmp->GetWidth( PADSTACK::ALL_LAYERS ) )
return aPadref->GetWidth( PADSTACK::ALL_LAYERS ) < aPadcmp->GetWidth( PADSTACK::ALL_LAYERS );
if( aPadref->GetDrillValue() != aPadcmp->GetDrillValue() )
return aPadref->GetDrillValue() < aPadcmp->GetDrillValue();
@ -302,10 +302,10 @@ void GENCAD_EXPORTER::CreatePadsShapesSection()
{
viastacks.push_back( via );
fprintf( m_file, "PAD V%d.%d.%s ROUND %g\nCIRCLE 0 0 %g\n",
via->GetWidth(), via->GetDrillValue(),
via->GetWidth( PADSTACK::ALL_LAYERS ), via->GetDrillValue(),
fmt_mask( via->GetLayerSet() & master_layermask ).c_str(),
via->GetDrillValue() / SCALE_FACTOR,
via->GetWidth() / (SCALE_FACTOR * 2) );
via->GetWidth( PADSTACK::ALL_LAYERS ) / (SCALE_FACTOR * 2) );
}
// Emit component pads
@ -554,14 +554,14 @@ void GENCAD_EXPORTER::CreatePadsShapesSection()
LSET mask = via->GetLayerSet() & master_layermask;
fprintf( m_file, "PADSTACK VIA%d.%d.%s %g\n",
via->GetWidth(), via->GetDrillValue(),
via->GetWidth( PADSTACK::ALL_LAYERS ), via->GetDrillValue(),
fmt_mask( mask ).c_str(),
via->GetDrillValue() / SCALE_FACTOR );
for( PCB_LAYER_ID layer : mask.Seq( gc_seq ) )
{
fprintf( m_file, "PAD V%d.%d.%s %s 0 0\n",
via->GetWidth(), via->GetDrillValue(),
via->GetWidth( PADSTACK::ALL_LAYERS ), via->GetDrillValue(),
fmt_mask( mask ).c_str(),
GenCADLayerName( cu_count, layer ).c_str() );
}
@ -984,7 +984,7 @@ void GENCAD_EXPORTER::CreateRoutesSection()
LSET vset = via->GetLayerSet() & master_layermask;
fprintf( m_file, "VIA VIA%d.%d.%s %g %g ALL %g via%d\n",
via->GetWidth(), via->GetDrillValue(),
via->GetWidth( PADSTACK::ALL_LAYERS ), via->GetDrillValue(),
fmt_mask( vset ).c_str(),
MapXTo( via->GetStart().x ), MapYTo( via->GetStart().y ),
via->GetDrillValue() / SCALE_FACTOR, vianum++ );

4
pcbnew/exporters/export_hyperlynx.cpp
View File

@ -233,8 +233,8 @@ HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PAD* aPad )
HYPERLYNX_PAD_STACK::HYPERLYNX_PAD_STACK( BOARD* aBoard, const PCB_VIA* aVia )
{
m_board = aBoard;
m_sx = aVia->GetWidth();
m_sy = aVia->GetWidth();
// TODO(JE) padstacks
m_sx = m_sy = aVia->GetWidth( PADSTACK::ALL_LAYERS );
m_angle = 0;
m_layers = aVia->GetLayerSet();
m_drill = aVia->GetDrillValue();

11
pcbnew/pad.cpp
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@ -1345,11 +1345,11 @@ bool PAD::HitTest( const VECTOR2I& aPosition, int aAccuracy ) const
Padstack().ForEachUniqueLayer(
[&]( PCB_LAYER_ID l )
{
if( GetEffectivePolygon( l, ERROR_INSIDE )->Contains( aPosition, -1, aAccuracy ) )
{
contains = true;
if( contains )
return;
}
if( GetEffectivePolygon( l, ERROR_INSIDE )->Contains( aPosition, -1, aAccuracy ) )
contains = true;
} );
return contains;
@ -1380,6 +1380,9 @@ bool PAD::HitTest( const BOX2I& aRect, bool aContained, int aAccuracy ) const
Padstack().ForEachUniqueLayer(
[&]( PCB_LAYER_ID aLayer )
{
if( hit )
return;
const std::shared_ptr<SHAPE_POLY_SET>& poly =
GetEffectivePolygon( aLayer, ERROR_INSIDE );

3
pcbnew/pcb_io/altium/altium_pcb.cpp
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@ -3829,7 +3829,8 @@ void ALTIUM_PCB::ParseVias6Data( const ALTIUM_PCB_COMPOUND_FILE& aAltiumPcbF
std::unique_ptr<PCB_VIA> via = std::make_unique<PCB_VIA>( m_board );
via->SetPosition( elem.position );
via->SetWidth( elem.diameter );
// TODO(JE) padstacks
via->SetWidth( PADSTACK::ALL_LAYERS, elem.diameter );
via->SetDrill( elem.holesize );
via->SetNetCode( GetNetCode( elem.net ) );
via->SetLocked( elem.is_locked );

4
pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp
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@ -2603,7 +2603,7 @@ int CADSTAR_PCB_ARCHIVE_LOADER::loadNetVia(
(double) ( (double) getKiCadLength( csViaCode.Shape.Size ) / 1E6 ) );
}
via->SetWidth( getKiCadLength( csViaCode.Shape.Size ) );
via->SetWidth( PADSTACK::ALL_LAYERS, getKiCadLength( csViaCode.Shape.Size ) );
bool start_layer_outside =
csLayerPair.PhysicalLayerStart == 1
@ -2630,7 +2630,7 @@ int CADSTAR_PCB_ARCHIVE_LOADER::loadNetVia(
via->SetNet( getKiCadNet( aCadstarNetID ) );
///todo add netcode to the via
return via->GetWidth();
return via->GetWidth( PADSTACK::ALL_LAYERS );
}

17
pcbnew/pcb_io/eagle/pcb_io_eagle.cpp
View File

@ -2812,7 +2812,7 @@ void PCB_IO_EAGLE::loadSignals( wxXmlNode* aSignals )
if( v.diam )
{
kidiam = v.diam->ToPcbUnits();
via->SetWidth( kidiam );
via->SetWidth( PADSTACK::ALL_LAYERS, kidiam );
}
else
{
@ -2820,20 +2820,21 @@ void PCB_IO_EAGLE::loadSignals( wxXmlNode* aSignals )
annulus = eagleClamp( m_rules->rlMinViaOuter, annulus,
m_rules->rlMaxViaOuter );
kidiam = KiROUND( drillz + 2 * annulus );
via->SetWidth( kidiam );
via->SetWidth( PADSTACK::ALL_LAYERS, kidiam );
}
via->SetDrill( drillz );
// make sure the via diameter respects the restring rules
if( !v.diam || via->GetWidth() <= via->GetDrill() )
if( !v.diam || via->GetWidth( PADSTACK::ALL_LAYERS ) <= via->GetDrill() )
{
double annulus =
eagleClamp( m_rules->rlMinViaOuter,
(double) ( via->GetWidth() / 2 - via->GetDrill() ),
m_rules->rlMaxViaOuter );
via->SetWidth( drillz + 2 * annulus );
double annulus = eagleClamp(
m_rules->rlMinViaOuter,
static_cast<double>( via->GetWidth( PADSTACK::ALL_LAYERS ) / 2
- via->GetDrill() ),
m_rules->rlMaxViaOuter );
via->SetWidth( PADSTACK::ALL_LAYERS, drillz + 2 * annulus );
}
if( kidiam < m_min_via )

2
pcbnew/pcb_io/easyeda/pcb_io_easyeda_parser.cpp
View File

@ -863,7 +863,7 @@ void PCB_IO_EASYEDA_PARSER::ParseToBoardItemContainer(
via->SetPosition( center );
via->SetWidth( kdia );
via->SetWidth( PADSTACK::ALL_LAYERS, kdia );
via->SetNet( getOrAddNetItem( arr[4] ) );
via->SetDrill( kdrill );

2
pcbnew/pcb_io/easyedapro/pcb_io_easyedapro_parser.cpp
View File

@ -1063,7 +1063,7 @@ void PCB_IO_EASYEDAPRO_PARSER::ParseBoard(
via->SetPosition( ScalePos( center ) );
via->SetDrill( ScaleSize( drill ) );
via->SetWidth( ScaleSize( dia ) );
via->SetWidth( PADSTACK::ALL_LAYERS, ScaleSize( dia ) );
via->SetNet( aBoard->FindNet( netname ) );

6
pcbnew/pcb_io/fabmaster/import_fabmaster.cpp
View File

@ -2526,19 +2526,19 @@ bool FABMASTER::loadVias( BOARD* aBoard )
if( !ds.m_ViasDimensionsList.empty() )
{
new_via->SetWidth( ds.m_ViasDimensionsList[0].m_Diameter );
new_via->SetWidth( PADSTACK::ALL_LAYERS, ds.m_ViasDimensionsList[0].m_Diameter );
new_via->SetDrill( ds.m_ViasDimensionsList[0].m_Drill );
}
else
{
new_via->SetDrillDefault();
new_via->SetWidth( ds.m_ViasMinSize );
new_via->SetWidth( PADSTACK::ALL_LAYERS, ds.m_ViasMinSize );
}
}
else
{
new_via->SetDrill( padstack->second.drill_size_x );
new_via->SetWidth( padstack->second.width );
new_via->SetWidth( PADSTACK::ALL_LAYERS, padstack->second.width );
}
aBoard->Add( new_via, ADD_MODE::APPEND );

4
pcbnew/pcb_io/ipc2581/pcb_io_ipc2581.cpp
View File

@ -1671,7 +1671,7 @@ void PCB_IO_IPC2581::addVia( wxXmlNode* aContentNode, const PCB_VIA* aVia, PCB_L
int hole = aVia->GetDrillValue();
dummy.SetDrillSize( VECTOR2I( hole, hole ) );
dummy.SetPosition( aVia->GetStart() );
dummy.SetSize( PADSTACK::ALL_LAYERS, VECTOR2I( aVia->GetWidth(), aVia->GetWidth() ) );
dummy.SetSize( aLayer, VECTOR2I( aVia->GetWidth( aLayer ), aVia->GetWidth( aLayer ) ) );
addShape( padNode, dummy, aLayer );
}
@ -1777,7 +1777,7 @@ void PCB_IO_IPC2581::addPadStack( wxXmlNode* aContentNode, const PCB_VIA* aVia )
PCB_SHAPE shape( nullptr, SHAPE_T::CIRCLE );
shape.SetEnd( { KiROUND( aVia->GetWidth() / 2.0 ), 0 } );
shape.SetEnd( { KiROUND( aVia->GetWidth( layer ) / 2.0 ), 0 } );
wxXmlNode* padStackPadDefNode = appendNode( padStackDefNode, "PadstackPadDef" );
addAttribute( padStackPadDefNode, "layerRef", m_layer_name_map[layer] );

5
pcbnew/pcb_io/kicad_legacy/pcb_io_kicad_legacy.cpp
View File

@ -2231,12 +2231,11 @@ void PCB_IO_KICAD_LEGACY::loadTrackList( int aStructType )
newTrack->SetPosition( VECTOR2I( start_x, start_y ) );
newTrack->SetEnd( VECTOR2I( end_x, end_y ) );
newTrack->SetWidth( width );
if( makeType == PCB_VIA_T ) // Ensure layers are OK when possible:
{
PCB_VIA *via = static_cast<PCB_VIA*>( newTrack );
via->SetViaType( viatype );
via->SetWidth( PADSTACK::ALL_LAYERS, width );
if( drill < 0 )
via->SetDrillDefault();
@ -2266,6 +2265,8 @@ void PCB_IO_KICAD_LEGACY::loadTrackList( int aStructType )
}
else
{
newTrack->SetWidth( width );
// A few legacy boards can have tracks on non existent layers, because
// reducing the number of layers does not remove tracks on removed layers
// If happens, skip them

37
pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp
View File

@ -2489,7 +2489,42 @@ void PCB_IO_KICAD_SEXPR::format( const PCB_TRACK* aTrack, int aNestLevel ) const
m_out->Print( 0, ")" );
}
formatTenting( via->Padstack() );
const PADSTACK& padstack = via->Padstack();
formatTenting( padstack );
if( padstack.Mode() != PADSTACK::MODE::NORMAL )
{
std::string mode =
padstack.Mode() == PADSTACK::MODE::CUSTOM ? "custom" : "front_inner_back";
m_out->Print( 0, "(padstack (mode %s)", mode.c_str() );
if( padstack.Mode() == PADSTACK::MODE::FRONT_INNER_BACK )
{
m_out->Print( 0, "(layer \"Inner\"" );
m_out->Print( 0, " (size %s)",
formatInternalUnits( padstack.Size( PADSTACK::INNER_LAYERS ).x ).c_str() );
m_out->Print( 0, ")(layer \"B.Cu\"" );
m_out->Print( 0, " (size %s)",
formatInternalUnits( padstack.Size( B_Cu ).x ).c_str() );
m_out->Print( 0, ")" );
}
else
{
for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu, board->GetCopperLayerCount() ) )
{
if( layer == F_Cu )
continue;
m_out->Print( 0, "(layer %s", m_out->Quotew( LSET::Name( layer ) ).c_str() );
m_out->Print( 0, " (size %s)",
formatInternalUnits( padstack.Size( layer ).x ).c_str() );
m_out->Print( 0, ")" );
}
}
m_out->Print( 0, ")" );
}
if( !isDefaultTeardropParameters( via->GetTeardropParams() ) )
{

3
pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
View File

@ -164,7 +164,8 @@ class PCB_IO_KICAD_SEXPR; // forward decl
//#define SEXPR_BOARD_FILE_VERSION 20240706 // Embedded Files
//#define SEXPR_BOARD_FILE_VERSION 20240819 // Embedded Files - Update hash algorithm to Murmur3
//#define SEXPR_BOARD_FILE_VERSION 20240928 // Component classes
#define SEXPR_BOARD_FILE_VERSION 20240929 // Complex padstacks
//#define SEXPR_BOARD_FILE_VERSION 20240929 // Complex padstacks
#define SEXPR_BOARD_FILE_VERSION 20241006 // Via stacks
#define BOARD_FILE_HOST_VERSION 20200825 ///< Earlier files than this include the host tag
#define LEGACY_ARC_FORMATTING 20210925 ///< These were the last to use old arc formatting

103
pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
View File

@ -6262,7 +6262,7 @@ PCB_VIA* PCB_IO_KICAD_SEXPR_PARSER::parsePCB_VIA()
break;
case T_size:
via->SetWidth( parseBoardUnits( "via width" ) );
via->SetWidth( PADSTACK::ALL_LAYERS, parseBoardUnits( "via width" ) );
NeedRIGHT();
break;
@ -6333,6 +6333,10 @@ PCB_VIA* PCB_IO_KICAD_SEXPR_PARSER::parsePCB_VIA()
}
break;
case T_padstack:
parseViastack( via.get() );
break;
case T_teardrops:
parseTEARDROP_PARAMETERS( &via->GetTeardropParams() );
break;
@ -6393,6 +6397,103 @@ void PCB_IO_KICAD_SEXPR_PARSER::parseTenting( PADSTACK& aPadstack )
}
void PCB_IO_KICAD_SEXPR_PARSER::parseViastack( PCB_VIA* aVia )
{
PADSTACK& padstack = aVia->Padstack();
for( T token = NextTok(); token != T_RIGHT; token = NextTok() )
{
if( token != T_LEFT )
Expecting( T_LEFT );
token = NextTok();
switch( token )
{
case T_mode:
token = NextTok();
switch( token )
{
case T_front_inner_back:
padstack.SetMode( PADSTACK::MODE::FRONT_INNER_BACK );
break;
case T_custom:
padstack.SetMode( PADSTACK::MODE::CUSTOM );
break;
default:
Expecting( "front_inner_back or custom" );
}
NeedRIGHT();
break;
case T_layer:
{
NextTok();
PCB_LAYER_ID curLayer = UNDEFINED_LAYER;
if( curText == "Inner" )
{
if( padstack.Mode() != PADSTACK::MODE::FRONT_INNER_BACK )
{
THROW_IO_ERROR( wxString::Format( _( "Invalid padstack layer in\nfile: %s\n"
"line: %d\noffset: %d." ),
CurSource(), CurLineNumber(), CurOffset() ) );
}
curLayer = PADSTACK::INNER_LAYERS;
}
else
{
curLayer = lookUpLayer( m_layerIndices );
}
if( !IsCopperLayer( curLayer ) )
{
wxString error;
error.Printf( _( "Invalid padstack layer '%s' in file '%s' at line %d, offset %d." ),
curText, CurSource().GetData(), CurLineNumber(), CurOffset() );
THROW_IO_ERROR( error );
}
for( token = NextTok(); token != T_RIGHT; token = NextTok() )
{
if( token != T_LEFT )
Expecting( T_LEFT );
token = NextTok();
switch( token )
{
case T_size:
{
int diameter = parseBoardUnits( "via width" );
padstack.SetSize( { diameter, diameter }, curLayer );
NeedRIGHT();
break;
}
default:
// Currently only supporting custom via diameter per layer, not other properties
Expecting( "size" );
}
}
break;
}
default:
Expecting( "mode or layer" );
break;
}
}
}
ZONE* PCB_IO_KICAD_SEXPR_PARSER::parseZONE( BOARD_ITEM_CONTAINER* aParent )
{
wxCHECK_MSG( CurTok() == T_zone, nullptr,

1
pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.h
View File

@ -237,6 +237,7 @@ private:
PCB_ARC* parseARC();
PCB_TRACK* parsePCB_TRACK();
PCB_VIA* parsePCB_VIA();
void parseViastack( PCB_VIA* aVia );
ZONE* parseZONE( BOARD_ITEM_CONTAINER* aParent );
PCB_TARGET* parsePCB_TARGET();
BOARD* parseBOARD();

4
pcbnew/pcb_io/odbpp/odb_feature.cpp
View File

@ -406,7 +406,7 @@ void FEATURES_MANAGER::InitFeatureList( PCB_LAYER_ID aLayer, std::vector<BOARD_I
AddFeatureAttribute(
*m_featuresList.back(),
ODB_ATTR::GEOMETRY{ "VIA_RoundD"
+ std::to_string( via->GetWidth() ) } );
+ std::to_string( via->GetWidth( aLayer ) ) } );
}
}
else
@ -428,7 +428,7 @@ void FEATURES_MANAGER::InitFeatureList( PCB_LAYER_ID aLayer, std::vector<BOARD_I
AddFeatureAttribute(
*m_featuresList.back(),
ODB_ATTR::GEOMETRY{ "VIA_RoundD"
+ std::to_string( via->GetWidth() ) } );
+ std::to_string( via->GetWidth( aLayer ) ) } );
}
}
}

2
pcbnew/pcb_io/pcad/pcad_pad.cpp
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@ -359,7 +359,7 @@ void PCAD_PAD::AddToBoard( FOOTPRINT* aFootprint )
via->SetPosition( VECTOR2I( m_PositionX, m_PositionY ) );
via->SetEnd( VECTOR2I( m_PositionX, m_PositionY ) );
via->SetWidth( height );
via->SetWidth( PADSTACK::ALL_LAYERS, height );
via->SetViaType( VIATYPE::THROUGH );
via->SetLayerPair( F_Cu, B_Cu );
via->SetDrill( m_Hole );

14
pcbnew/pcb_painter.cpp
View File

@ -936,6 +936,7 @@ void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
if( color == COLOR4D::CLEAR )
return;
PCB_LAYER_ID currentLayer = ToLAYER_ID( aLayer );
PCB_LAYER_ID layerTop, layerBottom;
aVia->LayerPair( &layerTop, &layerBottom );
@ -958,7 +959,7 @@ void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
return;
double maxSize = PCB_RENDER_SETTINGS::MAX_FONT_SIZE;
double size = aVia->GetWidth();
double size = aVia->GetWidth( currentLayer );
// Font size limits
if( size > maxSize )
@ -1106,12 +1107,12 @@ void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
m_gal->SetIsStroke( false );
m_gal->SetLineWidth( margin );
m_gal->DrawCircle( center, aVia->GetWidth() / 2.0 + margin );
m_gal->DrawCircle( center, aVia->GetWidth( currentLayer ) / 2.0 + margin );
}
else if( m_pcbSettings.IsPrinting() || IsCopperLayer( aLayer ) )
{
int annular_width = ( aVia->GetWidth() - getViaDrillSize( aVia ) ) / 2.0;
double radius = aVia->GetWidth() / 2.0;
int annular_width = ( aVia->GetWidth( currentLayer ) - getViaDrillSize( aVia ) ) / 2.0;
double radius = aVia->GetWidth( currentLayer ) / 2.0;
bool draw = false;
if( m_pcbSettings.IsPrinting() )
@ -1143,7 +1144,8 @@ void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
{
m_gal->SetLineWidth( m_lockedShadowMargin );
m_gal->DrawCircle( center, ( aVia->GetWidth() + m_lockedShadowMargin ) / 2.0 );
m_gal->DrawCircle( center,
( aVia->GetWidth( currentLayer ) + m_lockedShadowMargin ) / 2.0 );
}
// Clearance lines
@ -1165,7 +1167,7 @@ void PCB_PAINTER::draw( const PCB_VIA* aVia, int aLayer )
double radius;
if( aVia->FlashLayer( activeLayer ) )
radius = aVia->GetWidth() / 2.0;
radius = aVia->GetWidth( activeLayer ) / 2.0;
else
radius = getViaDrillSize( aVia ) / 2.0 + m_holePlatingThickness;

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