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Ensure deterministic ordering in cadstar netlist exporter
Also re-enable checking of exporter in qa_cli
This commit is contained in:
JamesJCode
parent
a3f69046ba
commit
3a7aa7b660
eeschema/netlist_exporters
qa
@ -67,7 +67,23 @@ bool NETLIST_EXPORTER_CADSTAR::WriteNetlist( const wxString& aOutFileName,
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for( const SCH_SHEET_PATH& sheet : m_schematic->Hierarchy() )
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{
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for( SCH_ITEM* item : sheet.LastScreen()->Items().OfType( SCH_SYMBOL_T ) )
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// The rtree returns items in a non-deterministic order (platform-dependent)
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// Therefore we need to sort them before outputting to ensure file stability for version
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// control and QA comparisons
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std::vector<EDA_ITEM*> sheetItems;
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for( EDA_ITEM* item : sheet.LastScreen()->Items().OfType( SCH_SYMBOL_T ) )
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sheetItems.push_back( item );
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auto pred = []( const EDA_ITEM* item1, const EDA_ITEM* item2 )
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{
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return item1->m_Uuid < item2->m_Uuid;
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};
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std::sort( sheetItems.begin(), sheetItems.end(), pred );
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// Process symbol attributes
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for( EDA_ITEM* item : sheetItems )
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{
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symbol = findNextSymbol( item, sheet );
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@ -115,13 +131,16 @@ bool NETLIST_EXPORTER_CADSTAR::writeListOfNets( FILE* f )
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wxString InitNetDesc = StartLine + wxT( "ADD_TER" );
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wxString StartNetDesc = StartLine + wxT( "TER" );
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wxString InitNetDescLine;
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wxString netName;
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std::vector<std::pair<wxString, std::vector<std::pair<SCH_PIN*, SCH_SHEET_PATH>>>> all_nets;
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for( const auto& [ key, subgraphs ] : m_schematic->ConnectionGraph()->GetNetMap() )
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{
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wxString netName;
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netName.Printf( wxT( "\"%s\"" ), key.Name );
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std::vector<std::pair<SCH_PIN*, SCH_SHEET_PATH>> sorted_items;
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all_nets.emplace_back( netName, std::vector<std::pair<SCH_PIN*, SCH_SHEET_PATH>>{} );
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std::vector<std::pair<SCH_PIN*, SCH_SHEET_PATH>>& sorted_items = all_nets.back().second;
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for( CONNECTION_SUBGRAPH* subgraph : subgraphs )
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{
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@ -134,7 +153,7 @@ bool NETLIST_EXPORTER_CADSTAR::writeListOfNets( FILE* f )
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}
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}
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// Netlist ordering: Net name, then ref des, then pin name
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// Intra-net ordering: Ref des, then pin name
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std::sort( sorted_items.begin(), sorted_items.end(),
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[]( std::pair<SCH_PIN*, SCH_SHEET_PATH> a, std::pair<SCH_PIN*, SCH_SHEET_PATH> b )
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{
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@ -159,7 +178,17 @@ bool NETLIST_EXPORTER_CADSTAR::writeListOfNets( FILE* f )
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return ref_a == ref_b && a.first->GetShownNumber() == b.first->GetShownNumber();
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} ),
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sorted_items.end() );
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}
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// Inter-net ordering by net name
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std::sort( all_nets.begin(), all_nets.end(),
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[]( const auto& a, const auto& b )
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{
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return a.first < b.first;
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} );
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for( const auto& [netName, sorted_items] : all_nets )
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{
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print_ter = 0;
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for( const std::pair<SCH_PIN*, SCH_SHEET_PATH>& pair : sorted_items )
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@ -1,19 +1,22 @@
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.HEA
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.TIM 5/2/2023 8:59:04 PM
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.APP "Eeschema 7.99.0-893-g4a5939297b-dirty"
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.TIM 2024-12-20T00:07:25+0000
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.APP "Eeschema 8.99.0-3439-gc9d74d24f0-dirty"
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.TYP FULL
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.ADD_COM R1 "10k" "Resistor_SMD:R_1206_3216Metric"
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.ADD_COM J1 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM J2 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM J4 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM C1 "10u" "Capacitor_SMD:C_1206_3216Metric"
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.ADD_COM R2 "10k" "Resistor_SMD:R_1206_3216Metric"
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.ADD_COM J3 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM J2 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM J1 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM J4 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM R3 "10k" "Resistor_SMD:R_1206_3216Metric"
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.ADD_COM J3 "Conn_01x01_Pin" "TestPoint:TestPoint_Pad_3.0x3.0mm"
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.ADD_COM U1 "TLV2371DBV" "Package_TO_SOT_SMD:SOT-23-5"
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.ADD_COM R1 "10k" "Resistor_SMD:R_1206_3216Metric"
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.ADD_TER J2 1 "/IN"
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.TER R3 1
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.ADD_TER J3 1 "/OUT"
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.TER R2 2
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U1 1
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@ -21,6 +24,11 @@
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.ADD_TER J1 1 "/VCC"
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.TER U1 5
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.ADD_TER C1 2 "GND"
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.TER J4 1
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R1 1
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U1 2
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.ADD_TER C1 1 "Net-(U1-+)"
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.TER R3 2
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U1 3
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@ -29,12 +37,4 @@
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.TER R2 1
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U1 4
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.ADD_TER C1 2 "GND"
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.TER J4 1
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R1 1
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U1 2
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.ADD_TER J2 1 "/IN"
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.TER R3 1
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.END
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@ -75,8 +75,7 @@ def test_sch_export_svg( kitest,
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[("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.kicadsexpr", 5, True, []),
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("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.kicadsexpr", 5, True,["--format=kicadsexpr"]),
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("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.kicadxml", 6, True,["--format=kicadxml"]),
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# currently inconsistenly sorts nets between platforms (MSW/Linux)
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("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.cadstar", 3, True, ["--format=cadstar"]),
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("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.cadstar", 3, False, ["--format=cadstar"]),
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("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.orcadpcb2", 1, False, ["--format=orcadpcb2"])
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])
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def test_sch_export_netlist( kitest,
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