7
mirror of https://gitlab.com/kicad/code/kicad.git synced 2025-04-07 18:35:32 +00:00

Measure distance from pad center, not pad hull.

Otherwise we think the wrong end of really short track segments is
connected to the pad, leaving the other end dangling.

Fixes https://gitlab.com/kicad/code/kicad/issues/8909
This commit is contained in:
Jeff Young 2021-08-02 22:41:59 +01:00
parent 8b9161b27d
commit 43523df843
4 changed files with 38 additions and 19 deletions

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@ -36,6 +36,7 @@
#include <connectivity/from_to_cache.h>
#include <ratsnest/ratsnest_data.h>
#include <trigo.h>
CONNECTIVITY_DATA::CONNECTIVITY_DATA()
{
@ -586,6 +587,25 @@ void CONNECTIVITY_DATA::GetUnconnectedEdges( std::vector<CN_EDGE>& aEdges) const
}
static int getMinDist( BOARD_CONNECTED_ITEM* aItem, const wxPoint& aPoint )
{
switch( aItem->Type() )
{
case PCB_TRACE_T:
case PCB_ARC_T:
{
PCB_TRACK* track = static_cast<PCB_TRACK*>( aItem );
return std::min( GetLineLength( track->GetStart(), aPoint ),
GetLineLength( track->GetEnd(), aPoint ) );
}
default:
return GetLineLength( aItem->GetPosition(), aPoint );
}
}
bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* aPos )
{
std::list<CN_ITEM*> items = GetConnectivityAlgo()->ItemEntry( aTrack ).GetItems();
@ -623,14 +643,12 @@ bool CONNECTIVITY_DATA::TestTrackEndpointDangling( PCB_TRACK* aTrack, wxPoint* a
std::shared_ptr<SHAPE> shape = item->GetEffectiveShape( layer );
int startDist;
int endDist;
bool hitStart = shape->Collide( aTrack->GetStart(), accuracy, &startDist );
bool hitEnd = shape->Collide( aTrack->GetEnd(), accuracy, &endDist );
bool hitStart = shape->Collide( aTrack->GetStart(), accuracy );
bool hitEnd = shape->Collide( aTrack->GetEnd(), accuracy );
if( hitStart && hitEnd )
{
if( startDist <= endDist )
if( getMinDist( item, aTrack->GetStart() ) < getMinDist( item, aTrack->GetEnd() ) )
start_count++;
else
end_count++;

View File

@ -147,7 +147,6 @@ const VECTOR2I CN_ITEM::GetAnchor( int n ) const
default:
assert( false );
break;
}
return pt0;

qa/data/issue6879.kicad_pcb
Executable file → Normal file
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LOADING design file

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@ -88,12 +88,12 @@
"silk_overlap": "error",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "ignore",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "ignore",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},