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https://gitlab.com/kicad/code/kicad.git
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Update some demos
This commit is contained in:
parent
b7a77a9498
commit
4bd349d922
demos/simulation
laser_driver
pspice
rectifier
sallen_key
subsheets
v_i_sources
eeschema/tools
@ -22,7 +22,8 @@
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"track_widths": [],
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"via_dimensions": []
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -280,6 +281,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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"default_line_thickness": 6.0,
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LOADING design file
LOADING design file
@ -6,7 +6,8 @@
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"track_widths": [],
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"via_dimensions": []
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -264,6 +265,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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"default_line_thickness": 6.0,
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LOADING design file
LOADING design file
@ -22,7 +22,8 @@
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"track_widths": [],
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"via_dimensions": []
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -280,6 +281,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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"default_line_thickness": 6.0,
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LOADING design file
LOADING design file
@ -116,7 +116,8 @@
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -374,6 +375,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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"default_line_thickness": 6.0,
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LOADING design file
LOADING design file
LOADING design file
LOADING design file
LOADING design file
@ -22,7 +22,8 @@
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"track_widths": [],
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"via_dimensions": []
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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@ -280,6 +281,8 @@
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"schematic": {
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"annotate_start_num": 0,
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_bus_thickness": 12.0,
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"default_junction_size": 40.0,
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"default_line_thickness": 6.0,
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LOADING design file
@ -1468,8 +1468,6 @@ int SCH_DRAWING_TOOLS::DrawShape( const TOOL_EVENT& aEvent )
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}
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else if( evt->IsClick( BUT_LEFT ) && !item )
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{
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EESCHEMA_SETTINGS* cfg = m_frame->eeconfig();
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m_toolMgr->RunAction( EE_ACTIONS::clearSelection, true );
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if( isTextBox )
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