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ADDED: DRC Checks for connected track angles

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This MR adds a new DRC Test provider for the angle between two connected Track segments.

Rule example:

(rule test_track_angle (constraint track_angle (min 135)) (severity error) )
This commit is contained in:
Daniel Treffenstädt 2024-10-16 19:16:42 +00:00 committed by Seth Hillbrand
parent 68b40f1ef3
commit 5e3c9334cc
13 changed files with 291 additions and 3 deletions

1
common/drc_rules.keywords
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@ -50,6 +50,7 @@ thermal_reliefs
thermal_relief_gap
thermal_spoke_width
track
track_angle
track_width
version
via

1
pcbnew/CMakeLists.txt
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@ -270,6 +270,7 @@ set( PCBNEW_DRC_SRCS
drc/drc_test_provider_schematic_parity.cpp
drc/drc_test_provider_misc.cpp
drc/drc_test_provider_text_dims.cpp
drc/drc_test_provider_track_angle.cpp
drc/drc_test_provider_track_width.cpp
drc/drc_test_provider_zone_connections.cpp
drc/drc_test_provider_via_diameter.cpp

2
pcbnew/dialogs/panel_setup_rules.cpp
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@ -264,6 +264,7 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
|| token == wxT( "thermal_relief_gap" )
|| token == wxT( "thermal_spoke_width" )
|| token == wxT( "track_width" )
|| token == wxT( "track_angle" )
|| token == wxT( "via_count" )
|| token == wxT( "via_diameter" )
|| token == wxT( "zone_connection" );
@ -480,6 +481,7 @@ void PANEL_SETUP_RULES::onScintillaCharAdded( wxStyledTextEvent &aEvent )
"thermal_relief_gap|"
"thermal_spoke_width|"
"track_width|"
"track_angle|"
"via_count|"
"via_diameter|"
"zone_connection" );

1
pcbnew/dialogs/panel_setup_rules_help.md
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@ -43,6 +43,7 @@
| `thermal_relief_gap` | min | Specifies the width of the gap between a pad and a zone with a thermal-relief connection.<br> |
| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> |
| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |
| `track_angle` | min/opt/max | Checks the angle between two connected track segments. An error will be generated for each connected pair with an angle below the `min` value (if specified) or above the `max` value (if specified).<br> |
| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> |
| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` | Specifies the connection to be made between a zone and a pad.<br> |

1
pcbnew/dialogs/panel_setup_rules_help_md.h
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@ -44,6 +44,7 @@ _HKI( "### Top-level Clauses\n"
"| `thermal_relief_gap` | min | Specifies the width of the gap between a pad and a zone with a thermal-relief connection.<br> |\n"
"| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> |\n"
"| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> |\n"
"| `track_angle` | min/opt/max | Checks the angle between two connected track segments. An error will be generated for each connected pair with an angle below the `min` value (if specified) or above the `max` value (if specified).<br> |\n"
"| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> |\n"
"| `zone_connection` | `solid`<br>`thermal_reliefs`<br>`none` | Specifies the connection to be made between a zone and a pad.<br> |\n"
"\n"

6
pcbnew/drc/drc_item.cpp
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@ -122,6 +122,10 @@ DRC_ITEM DRC_ITEM::trackWidth( DRCE_TRACK_WIDTH,
_( "Track width" ),
wxT( "track_width" ) );
DRC_ITEM DRC_ITEM::trackAngle( DRCE_TRACK_ANGLE,
_( "Track angle" ),
wxT( "track_angle" ) );
DRC_ITEM DRC_ITEM::annularWidth( DRCE_ANNULAR_WIDTH,
_( "Annular width" ),
wxT( "annular_width" ) );
@ -301,6 +305,7 @@ std::vector<std::reference_wrapper<RC_ITEM>> DRC_ITEM::allItemTypes(
DRC_ITEM::holeNearHole,
DRC_ITEM::holesCoLocated,
DRC_ITEM::trackWidth,
DRC_ITEM::trackAngle,
DRC_ITEM::annularWidth,
DRC_ITEM::drillTooSmall,
DRC_ITEM::microviaDrillTooSmall,
@ -381,6 +386,7 @@ std::shared_ptr<DRC_ITEM> DRC_ITEM::Create( int aErrorCode )
case DRCE_HOLE_CLEARANCE: return std::make_shared<DRC_ITEM>( holeClearance );
case DRCE_CONNECTION_WIDTH: return std::make_shared<DRC_ITEM>( connectionWidth );
case DRCE_TRACK_WIDTH: return std::make_shared<DRC_ITEM>( trackWidth );
case DRCE_TRACK_ANGLE: return std::make_shared<DRC_ITEM>( trackAngle );
case DRCE_ANNULAR_WIDTH: return std::make_shared<DRC_ITEM>( annularWidth );
case DRCE_DRILL_OUT_OF_RANGE: return std::make_shared<DRC_ITEM>( drillTooSmall );
case DRCE_VIA_DIAMETER: return std::make_shared<DRC_ITEM>( viaDiameter );

2
pcbnew/drc/drc_item.h
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@ -53,6 +53,7 @@ enum PCB_DRC_CODE {
DRCE_DRILLED_HOLES_COLOCATED, // two holes at the same location
DRCE_HOLE_CLEARANCE, //
DRCE_TRACK_WIDTH, // Track width is too small or too large
DRCE_TRACK_ANGLE, // Angle between two connected tracks is too small or too large
DRCE_ANNULAR_WIDTH, // Via size and drill leave annular ring too small
DRCE_CONNECTION_WIDTH, // Net connection too small
DRCE_DRILL_OUT_OF_RANGE, // Too small via or pad drill
@ -192,6 +193,7 @@ private:
static DRC_ITEM holeClearance;
static DRC_ITEM connectionWidth;
static DRC_ITEM trackWidth;
static DRC_ITEM trackAngle;
static DRC_ITEM annularWidth;
static DRC_ITEM drillTooSmall;
static DRC_ITEM viaDiameter;

3
pcbnew/drc/drc_rule.h
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@ -73,7 +73,8 @@ enum DRC_CONSTRAINT_T
PHYSICAL_CLEARANCE_CONSTRAINT,
PHYSICAL_HOLE_CLEARANCE_CONSTRAINT,
ASSERTION_CONSTRAINT,
CONNECTION_WIDTH_CONSTRAINT
CONNECTION_WIDTH_CONSTRAINT,
TRACK_ANGLE_CONSTRAINT
};

6
pcbnew/drc/drc_rule_parser.cpp
View File

@ -316,6 +316,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
case T_text_height: c.m_Type = TEXT_HEIGHT_CONSTRAINT; break;
case T_text_thickness: c.m_Type = TEXT_THICKNESS_CONSTRAINT; break;
case T_track_width: c.m_Type = TRACK_WIDTH_CONSTRAINT; break;
case T_track_angle: c.m_Type = TRACK_ANGLE_CONSTRAINT; break;
case T_connection_width: c.m_Type = CONNECTION_WIDTH_CONSTRAINT; break;
case T_annular_width: c.m_Type = ANNULAR_WIDTH_CONSTRAINT; break;
case T_via_diameter: c.m_Type = VIA_DIAMETER_CONSTRAINT; break;
@ -335,7 +336,7 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
msg.Printf( _( "Unrecognized item '%s'.| Expected %s." ), FromUTF8(),
wxT( "assertion, clearance, hole_clearance, edge_clearance, "
"physical_clearance, physical_hole_clearance, courtyard_clearance, "
"silk_clearance, hole_size, hole_to_hole, track_width, annular_width, "
"silk_clearance, hole_size, hole_to_hole, track_width, track_angle, annular_width, "
"disallow, zone_connection, thermal_relief_gap, thermal_spoke_width, "
"min_resolved_spokes, length, skew, via_count, via_diameter, "
"diff_pair_gap or diff_pair_uncoupled" ) );
@ -349,7 +350,8 @@ void DRC_RULES_PARSER::parseConstraint( DRC_RULE* aRule )
}
bool unitless = c.m_Type == VIA_COUNT_CONSTRAINT
|| c.m_Type == MIN_RESOLVED_SPOKES_CONSTRAINT;
|| c.m_Type == MIN_RESOLVED_SPOKES_CONSTRAINT
|| c.m_Type == TRACK_ANGLE_CONSTRAINT;
if( c.m_Type == DISALLOW_CONSTRAINT )
{

16
pcbnew/drc/drc_test_provider.cpp
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@ -366,3 +366,19 @@ wxString DRC_TEST_PROVIDER::formatMsg( const wxString& aFormatString, const wxSt
return wxString::Format( aFormatString, aSource, constraint_str, actual_str );
}
wxString DRC_TEST_PROVIDER::formatMsg( const wxString& aFormatString, const wxString& aSource,
const EDA_ANGLE& aConstraint, const EDA_ANGLE& aActual )
{
wxString constraint_str = MessageTextFromValue( aConstraint );
wxString actual_str = MessageTextFromValue( aActual );
if( constraint_str == actual_str )
{
// Use more precise formatting if the message-text strings were equal.
constraint_str = StringFromValue( aConstraint, true );
actual_str = StringFromValue( aActual, true );
}
return wxString::Format( aFormatString, aSource, constraint_str, actual_str );
}

2
pcbnew/drc/drc_test_provider.h
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@ -125,6 +125,8 @@ protected:
wxString formatMsg( const wxString& aFormatString, const wxString& aSource, double aConstraint,
double aActual );
wxString formatMsg( const wxString& aFormatString, const wxString& aSource,
const EDA_ANGLE& aConstraint, const EDA_ANGLE& aActual );
// List of basic (ie: non-compound) geometry items
static std::vector<KICAD_T> s_allBasicItems;

237
pcbnew/drc/drc_test_provider_track_angle.cpp Normal file
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@ -0,0 +1,237 @@
/*
* This program source code file is part of KiCad, a free EDA CAD application.
*
* Copyright (C) 2004-2023 KiCad Developers.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you may find one here:
* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
* or you may search the http://www.gnu.org website for the version 2 license,
* or you may write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include <core/thread_pool.h>
#include "geometry/eda_angle.h"
#include <numbers>
#include <pcb_track.h>
#include <drc/drc_engine.h>
#include <drc/drc_item.h>
#include <drc/drc_rule.h>
#include <drc/drc_test_provider.h>
#include <connectivity/connectivity_data.h>
/*
Track angle test. Checks the angle between two connected track segments.
Errors generated:
- DRCE_TRACK_ANGLE
*/
class DRC_TEST_PROVIDER_TRACK_ANGLE : public DRC_TEST_PROVIDER
{
public:
DRC_TEST_PROVIDER_TRACK_ANGLE()
{}
virtual ~DRC_TEST_PROVIDER_TRACK_ANGLE()
{}
virtual bool Run() override;
virtual const wxString GetName() const override
{
return wxT( "angle" );
};
virtual const wxString GetDescription() const override
{
return wxT( "Tests track angles" );
}
};
bool DRC_TEST_PROVIDER_TRACK_ANGLE::Run()
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TRACK_ANGLE ) )
{
reportAux( wxT( "Track angle violations ignored. Tests not run." ) );
return true; // continue with other tests
}
if( !m_drcEngine->HasRulesForConstraintType( TRACK_ANGLE_CONSTRAINT ) )
{
reportAux( wxT( "No track angle constraints found. Tests not run." ) );
return true; // continue with other tests
}
if( !reportPhase( _( "Checking track angles..." ) ) )
return false; // DRC cancelled
auto checkTrackAngle =
[&]( PCB_TRACK* item ) -> bool
{
if( m_drcEngine->IsErrorLimitExceeded( DRCE_TRACK_ANGLE ) )
{
return false;
}
if( item->Type() != PCB_TRACE_T )
{
return true;
}
SEG segment = SEG( item->GetStart(), item->GetEnd() );
std::shared_ptr<CONNECTIVITY_DATA> connectivity = m_drcEngine->GetBoard()->GetConnectivity();
for( PCB_TRACK* other : connectivity->GetConnectedTracks( item ) )
{
if( other->Type() != PCB_TRACE_T )
{
continue;
}
SEG other_segment = SEG( other->GetStart(), other->GetEnd() );
OPT_VECTOR2I intersection_opt = segment.Intersect( other_segment );
if( !intersection_opt.has_value() )
{
continue;
}
VECTOR2I p0 = intersection_opt.value();
if( m_drcEngine->GetBoard()->GetPad( p0, { item->GetLayer() } ) )
{
continue;
}
auto constraint = m_drcEngine->EvalRules( TRACK_ANGLE_CONSTRAINT, item, other,
item->GetLayer() );
VECTOR2D direction = VECTOR2D( item->GetEnd() - item->GetStart() ).Resize( 1 );
VECTOR2D other_direction = VECTOR2D( other->GetEnd() - other->GetStart() ).Resize( 1 );
EDA_ANGLE actual;
bool angle_below_90 = false;
if( segment.B == p0 )
{
direction *= -1;
}
else if( segment.A != p0 )
{
angle_below_90 = true;
}
if( other_segment.B == p0 )
{
other_direction *= -1;
}
else if( other_segment.A != p0 )
{
angle_below_90 = true;
}
actual = EDA_ANGLE::Arccos( direction.Dot( other_direction ) );
if( angle_below_90 && actual > 90 )
{
actual -= 90;
}
bool fail_min = false;
bool fail_max = false;
EDA_ANGLE constraintAngle = 0;
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
{
if( constraint.Value().HasMin() && actual.AsDegrees() < constraint.Value().Min() )
{
fail_min = true;
constraintAngle = EDA_ANGLE( constraint.Value().Min(), DEGREES_T );
}
if( constraint.Value().HasMax() && actual.AsDegrees() > constraint.Value().Max() )
{
fail_max = true;
constraintAngle = EDA_ANGLE( constraint.Value().Max(), DEGREES_T );
}
}
if( fail_min || fail_max )
{
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACK_ANGLE );
wxString constraintName = constraint.GetName();
wxString msg;
if( fail_min )
{
msg = formatMsg( _( "(%s min angle %s; actual %s)" ),
constraintName,
constraintAngle,
actual );
}
else
{
msg = formatMsg( _( "(%s max angle %s; actual %s)" ),
constraintName,
constraintAngle,
actual );
}
drcItem->SetErrorMessage( drcItem->GetErrorText() + wxS( " " ) + msg );
drcItem->SetItems( item , other );
drcItem->SetViolatingRule( constraint.GetParentRule() );
reportViolation( drcItem, p0, item->GetLayer() );
}
}
return true;
};
const int progressDelta = 250;
int ii = 0;
thread_pool& tp = GetKiCadThreadPool();
std::vector<std::future<bool>> returns;
returns.reserve( m_drcEngine->GetBoard()->Tracks().size() );
for( PCB_TRACK* item : m_drcEngine->GetBoard()->Tracks() )
{
returns.emplace_back( tp.submit( checkTrackAngle, item ) );
}
for( std::future<bool>& ret : returns )
{
std::future_status status = ret.wait_for( std::chrono::milliseconds( 250 ) );
while( status != std::future_status::ready )
{
reportProgress( ii++, m_drcEngine->GetBoard()->Tracks().size(), progressDelta );
status = ret.wait_for( std::chrono::milliseconds( 250 ) );
}
}
reportRuleStatistics();
return !m_drcEngine->IsCancelled();
}
namespace detail
{
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_TRACK_ANGLE> dummy;
}

16
pcbnew/tools/board_inspection_tool.cpp
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@ -309,6 +309,7 @@ wxString BOARD_INSPECTION_TOOL::InspectDRCErrorMenuText( const std::shared_ptr<R
|| aDRCItem->GetErrorCode() == DRCE_TEXT_THICKNESS
|| aDRCItem->GetErrorCode() == DRCE_DIFF_PAIR_UNCOUPLED_LENGTH_TOO_LONG
|| aDRCItem->GetErrorCode() == DRCE_TRACK_WIDTH
|| aDRCItem->GetErrorCode() == DRCE_TRACK_ANGLE
|| aDRCItem->GetErrorCode() == DRCE_VIA_DIAMETER
|| aDRCItem->GetErrorCode() == DRCE_ANNULAR_WIDTH
|| aDRCItem->GetErrorCode() == DRCE_DRILL_OUT_OF_RANGE
@ -440,6 +441,21 @@ void BOARD_INSPECTION_TOOL::InspectDRCError( const std::shared_ptr<RC_ITEM>& aDR
reportMin( m_frame, constraint ),
reportMax( m_frame, constraint ) ) );
break;
case DRCE_TRACK_ANGLE:
r = dialog->AddHTMLPage( _( "Track Angle" ) );
reportHeader( _( "Track Angle resolution for:" ), a, r );
if( compileError )
reportCompileError( r );
constraint = drcEngine->EvalRules( TRACK_ANGLE_CONSTRAINT, a, b, layer, r );
r->Report( "" );
r->Report( wxString::Format( _( "Resolved angle constraints: min %s; max %s." ),
reportMin( m_frame, constraint ),
reportMax( m_frame, constraint ) ) );
break;
case DRCE_CONNECTION_WIDTH:
r = dialog->AddHTMLPage( _( "Connection Width" ) );